jueves, 17 de julio de 2008

Current Processors Chart



AMD Desktop


Athlon 64 (Socket 754)
AMD
Processors		 Natural
State		 Sockets L1/L2 Cache
(Associativity)		 Transistors
Athlon 64 ??? MMX 3DNow! SSE SSE2
(Clawhammer)
(64-bit on-Die unbuffered DDR PC2700 mem controller; 4GB max)
[cancelled]		 754 pins
?MHz (200x?)
(64-bit dual-pumped bus)
?v		 Socket 754 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		 ? million
0.13µm process
104mm² die
AMD
Processors		 Natural
State		 Sockets L1/L2 Cache
(Associativity)		 Transistors
Athlon 64 2800+ MMX 3DNow! SSE SSE2
(Clawhammer)
(64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max)
March 30, 2004 - {$178}		 754 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
1.5v		 Socket 754 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		 106 million
0.13µm process
193mm² die
Athlon 64 3000+ MMX 3DNow! SSE SSE2
(Clawhammer)
(64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max)
December 15, 2003 - {$218}		 754 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.5v		 Socket 754 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		 106 million
0.13µm process
193mm² die
Athlon 64 3200+ MMX 3DNow! SSE SSE2
(Clawhammer)
(64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max)
September 23, 2003 - {$417}		 754 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.5v		 Socket 754 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 106 million
0.13µm process
193mm² die
Athlon 64 3400+ MMX 3DNow! SSE SSE2
(Clawhammer)
(64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max)
January 6, 2004 - {$417}		 754 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.5v		 Socket 754 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 106 million
0.13µm process
193mm² die
Athlon 64 3700+ MMX 3DNow! SSE SSE2
(Clawhammer)
(64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max)
June 1, 2004 - {$710}		 754 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.5v		 Socket 754 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 106 million
0.13µm process
193mm² die

Athlon 64 2800+ MMX 3DNow! SSE SSE2
(Newcastle)
(64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max)
July, 2004		 754 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
1.5v		 Socket 754 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		 68.5 million
0.13µm process
144mm² die
Athlon 64 3000+ MMX 3DNow! SSE SSE2
(Newcastle)
(64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max)
July, 2004 - {$218}		 754 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.5v		 Socket 754 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		 68.5 million
0.13µm process
144mm² die
Athlon 64 3200+ MMX 3DNow! SSE SSE2
(Newcastle)
(64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max)
July, 2004 - {$278}		 754 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.5v		 Socket 754 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		 68.5 million
0.13µm process
144mm² die
Athlon 64 3400+ MMX 3DNow! SSE SSE2
(Newcastle)
(64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max)
July, 2004 - {$417}		 754 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.5v		 Socket 754 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		 68.5 million
0.13µm process
144mm² die
AMD
Processors		 Natural
State		 Sockets L1/L2 Cache
(Associativity)		 Transistors
Sempron 2600+ MMX 3DNow! SSE SSE2
(Paris)
(64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max)
(32-bit only)
2005		 754 pins
1200MHz (200x6)
(64-bit dual-pumped bus)
1.5v		 Socket 754 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)		 ? million
0.13µm process
118mm² die
Sempron 2800+ MMX 3DNow! SSE SSE2
(Paris)
(64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max)
(32-bit only)
2005		 754 pins
1400MHz (200x7)
(64-bit dual-pumped bus)
1.5v		 Socket 754 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)		 ? million
0.13µm process
118mm² die
Sempron 3000+ MMX 3DNow! SSE SSE2
(Paris)
(64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max)
(32-bit only)
2005		 754 pins
1600MHz (200x8)
(64-bit dual-pumped bus)
1.5v		 Socket 754 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)		 ? million
0.13µm process
118mm² die
Sempron 3100+ MMX 3DNow! SSE SSE2
(Paris)
(64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max)
(32-bit only)
July 28, 2004 - {$126}		 754 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
1.5v		 Socket 754 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)		 ? million
0.13µm process
118mm² die
Sempron 3300+ MMX 3DNow! SSE SSE2
(Paris)
(64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max)
(32-bit only)
1Q 2005		 754 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.5v		 Socket 754 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)		 ? million
0.13µm process
118mm² die

Sempron 2500+ MMX 3DNow! SSE SSE2 SSE3
(Palermo)
(64-bit on-Die unbuffered DDR mem controller)
July 7, 2005		 754 pins
1400MHz (200x7)
(64-bit dual-pumped bus)
1.4v		 Socket 754 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)		 77 million
0.09µm process
84mm² die
Sempron 2600+ MMX 3DNow! SSE SSE2 SSE3
(Palermo)
(64-bit on-Die unbuffered DDR mem controller)
(32-bit only)
February 15, 2005		 754 pins
1600MHz (200x8)
(64-bit dual-pumped bus)
1.4v		 Socket 754 64KB data (2-way)
64KB instruction (2-way)
128KB on-Die unified L2 (16-way exclusive)		 77 million
0.09µm process
84mm² die
Sempron 2800+ MMX 3DNow! SSE SSE2 SSE3
(Palermo)
(64-bit on-Die unbuffered DDR mem controller)
(32-bit only)
February 15, 2005		 754 pins
1600MHz (200x8)
(64-bit dual-pumped bus)
1.4v		 Socket 754 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)		 77 million
0.09µm process
84mm² die
Sempron 3000+ MMX 3DNow! SSE SSE2 SSE3
(Palermo)
(64-bit on-Die unbuffered DDR mem controller)
(32-bit only)
February 15, 2005		 754 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
1.4v		 Socket 754 64KB data (2-way)
64KB instruction (2-way)
128KB on-Die unified L2 (16-way exclusive)		 77 million
0.09µm process
84mm² die
Sempron 3100+ MMX 3DNow! SSE SSE2 SSE3
(Palermo)
(64-bit on-Die unbuffered DDR mem controller)
(32-bit only)
February 15, 2005		 754 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
1.4v		 Socket 754 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)		 77 million
0.09µm process
84mm² die
Sempron 3300+ MMX 3DNow! SSE SSE2 SSE3
(Palermo)
(64-bit on-Die unbuffered DDR mem controller)
(32-bit only)
April 18, 2005		 754 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.4v		 Socket 754 64KB data (2-way)
64KB instruction (2-way)
128KB on-Die unified L2 (16-way exclusive)		 77 million
0.09µm process
84mm² die
Sempron 3400+ MMX 3DNow! SSE SSE2 SSE3
(Palermo)
(64-bit on-Die unbuffered DDR mem controller)
(32-bit only)
July 29, 2005 - {$134}		 754 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.4v		 Socket 754 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)		 77 million
0.09µm process
84mm² die


Athlon 64 (Socket 939)
AMD
Processors		 Natural
State		 Sockets L1/L2 Cache
(Associativity)		 Transistors
Athlon 64 2800+ MMX 3DNow! SSE SSE2
(Newcastle)
(128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max)
[not released]		 939 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
1.5v		 Socket 939 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		 68.5 million
0.13µm process
144mm² die
Athlon 64 3000+ MMX 3DNow! SSE SSE2
(Newcastle)
(128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max)
[not released]		 939 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.5v		 Socket 939 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		 68.5 million
0.13µm process
144mm² die
Athlon 64 3500+ MMX 3DNow! SSE SSE2
(Newcastle)
(128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max)
June 1, 2004 - {$500}		 939 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.5v		 Socket 939 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		 68.5 million
0.13µm process
144mm² die
Athlon 64 3800+ MMX 3DNow! SSE SSE2
(Newcastle)
(128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max)
June 1, 2004 - {$720}		 939 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.5v		 Socket 939 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		 68.5 million
0.13µm process
144mm² die

Athlon 64 4000+ MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max)
October 19, 2004 - {$729}		 939 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.5v		 Socket 939 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 106 million
0.13µm process
193mm² die

Athlon 64 4000+ MMX 3DNow! SSE SSE2 SSE3
(San Diego)
(128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max)
?		 939 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.4v		 Socket 939 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 114 million
0.09µm process
115mm² die

Athlon 64 ??? MMX 3DNow! SSE SSE2
(Victoria)
(128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max)
[cancelled]		 939 pins
?MHz (200x?)
(64-bit dual-pumped bus)
1.5v		 Socket 939 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)		 ? million
0.09µm process
?mm² die

Athlon 64 3000+ MMX 3DNow! SSE SSE2
(Winchester)
(128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max)
4Q 2004		 939 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
1.4v		 Socket 939 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		 68.5 million
0.09µm process
102mm² die
Athlon 64 3200+ MMX 3DNow! SSE SSE2
(Winchester)
(128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max)
4Q 2004		 939 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.4v		 Socket 939 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		 68.5 million
0.09µm process
102mm² die
Athlon 64 3500+ MMX 3DNow! SSE SSE2
(Winchester)
(128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max)
4Q 2004		 939 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.4v		 Socket 939 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		 68.5 million
0.09µm process
102mm² die
Athlon 64 4200+ MMX 3DNow! SSE SSE2
(Winchester)
(128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max)
[not released]		 939 pins
?MHz (200x?)
(64-bit dual-pumped bus)
1.4v		 Socket 939 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		 68.5 million
0.09µm process
102mm² die

Athlon 64 3000+ MMX 3DNow! SSE SSE2 SSE3
(Venice)
(128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max)
May, 2005		 939 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
?v		 Socket 939 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		 114 million
0.09µm process
~120mm² die
Athlon 64 3200+ MMX 3DNow! SSE SSE2 SSE3
(Venice)
(128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max)
May, 2005		 939 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
?v		 Socket 939 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		 114 million
0.09µm process
~120mm² die
Athlon 64 3500+ MMX 3DNow! SSE SSE2 SSE3
(Venice)
(128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max)
May, 2005		 939 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
?v		 Socket 939 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		 114 million
0.09µm process
~120mm² die
Athlon 64 3800+ MMX 3DNow! SSE SSE2 SSE3
(Venice)
(128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max)
May, 2005		 939 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
?v		 Socket 939 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		 114 million
0.09µm process
~120mm² die
AMD
Processors		 Natural
State		 Sockets L1/L2 Cache
(Associativity)		 Transistors
Athlon 64 X2 3800+ MMX 3DNow! SSE SSE2 SSE3
(Manchester)
(128-bit on-Die unbuffered DDR mem controller)
(dual core)
August 1, 2005 - {$354}		 939 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.4v		 Socket 939 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		 154 million
0.09µm process
~147mm² die
Athlon 64 X2 4200+ MMX 3DNow! SSE SSE2 SSE3
(Manchester)
(128-bit on-Die unbuffered DDR mem controller)
(dual core)
May 31, 2005 - {$537}		 939 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.4v		 Socket 939 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		 154 million
0.09µm process
~147mm² die
Athlon 64 X2 4600+ MMX 3DNow! SSE SSE2 SSE3
(Manchester)
(128-bit on-Die unbuffered DDR mem controller)
(dual core)
May 31, 2005 - {$803}		 939 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.4v		 Socket 939 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		 154 million
0.09µm process
~147mm² die

Athlon 64 X2 4400+ MMX 3DNow! SSE SSE2 SSE3
(Toledo)
(128-bit on-Die unbuffered DDR mem controller)
(dual core)
May 31, 2005 - {$581}		 939 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.4v		 Socket 939 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 233 million
0.09µm process
~199mm² die
Athlon 64 X2 4800+ MMX 3DNow! SSE SSE2 SSE3
(Toledo)
(128-bit on-Die unbuffered DDR mem controller)
(dual core)
May 31, 2005 - {$1001}		 939 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.4v		 Socket 939 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 233 million
0.09µm process
~199mm² die
AMD
Processors		 Natural
State		 Sockets L1/L2 Cache
(Associativity)		 Transistors
Sempron 3000+ MMX 3DNow! SSE SSE2
(Palermo)
(128-bit on-Die unbuffered DDR mem controller)
June, 2006		 939 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
1.4v		 Socket 939 64KB data (2-way)
64KB instruction (2-way)
128KB on-Die unified L2 (16-way exclusive)		 77 million
0.09µm process
84mm² die
Sempron 3200+ MMX 3DNow! SSE SSE2
(Palermo)
(128-bit on-Die unbuffered DDR mem controller)
June, 2006		 939 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
1.4v		 Socket 939 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)		 77 million
0.09µm process
84mm² die
Sempron 3400+ MMX 3DNow! SSE SSE2
(Palermo)
(128-bit on-Die unbuffered DDR mem controller)
June, 2006		 939 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.4v		 Socket 939 64KB data (2-way)
64KB instruction (2-way)
128KB on-Die unified L2 (16-way exclusive)		 77 million
0.09µm process
84mm² die
Sempron 3500+ MMX 3DNow! SSE SSE2
(Palermo)
(128-bit on-Die unbuffered DDR mem controller)
June, 2006		 939 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.4v		 Socket 939 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)		 77 million
0.09µm process
84mm² die


Athlon 64 (Socket AM2 / AM3)
(NOT compatible with Socket 940 CPUs!)
AMD
Processors		 Natural
State		 Sockets L1/L2 Cache
(Associativity)		 Transistors
Athlon 64 LE 1600 MMX 3DNow! SSE SSE2 SSE3
(Orleans)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
2007		 940 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.4v		 Socket AM2
Socket AM2+		 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 81 million
0.09µm process
103mm² die
Athlon 64 LE 1620 MMX 3DNow! SSE SSE2 SSE3
(Orleans)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
2007		 940 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.4v		 Socket AM2
Socket AM2+		 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 81 million
0.09µm process
103mm² die
Athlon 64 LE 1640 MMX 3DNow! SSE SSE2 SSE3
(Orleans)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
2008?		 940 pins
2700MHz (200x13.5)
(64-bit dual-pumped bus)
1.4v		 Socket AM2
Socket AM2+		 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		 81 million
0.09µm process
103mm² die
Athlon 64 3000+ MMX 3DNow! SSE SSE2 SSE3
(Orleans)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
May 23, 2006		 940 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
1.4v		 Socket AM2
Socket AM2+		 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		 81 million
0.09µm process
103mm² die
Athlon 64 3200+ MMX 3DNow! SSE SSE2 SSE3
(Orleans)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
May 23, 2006		 940 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.4v		 Socket AM2
Socket AM2+		 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		 81 million
0.09µm process
103mm² die
Athlon 64 3500+ MMX 3DNow! SSE SSE2 SSE3
(Orleans)
(128-bit on-Die unbuffered DDR2 PC5800 mem controller; 8GB max)
May 23, 2006 - {$189}		 940 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.25v or 1.4v		 Socket AM2
Socket AM2+		 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		 81 million
0.09µm process
103mm² die
Athlon 64 3800+ MMX 3DNow! SSE SSE2 SSE3
(Orleans)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
May 23, 2006 - {$290}		 940 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.4v		 Socket AM2
Socket AM2+		 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		 81 million
0.09µm process
103mm² die
Athlon 64 4000+ MMX 3DNow! SSE SSE2 SSE3
(Orleans)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
February 20, 2007 - {$102}		 940 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
1.4v		 Socket AM2
Socket AM2+		 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		 81 million
0.09µm process
103mm² die

Athlon 64 3500+ EE MMX 3DNow! SSE SSE2 SSE3
(Lima)
(128-bit on-Die unbuffered DDR2 PC5800 mem controller; 8GB max)
February 20, 2007 - {$88}		 940 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.35v		 Socket AM2
Socket AM2+		 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		 77 million
0.065µm process
?mm² die
Athlon 64 3800+ EE MMX 3DNow! SSE SSE2 SSE3
(Lima)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
February 20, 2007 - {$93}		 940 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.4v		 Socket AM2
Socket AM2+		 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		 77 million
0.065µm process
?mm² die
AMD
Processors		 Natural
State		 Sockets L1/L2 Cache
(Associativity)		 Transistors
Athlon 64 X2 3800+ MMX 3DNow! SSE SSE2 SSE3
(Windsor)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
(dual core)
May 23, 2006 - {$303}		 940 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.075v or 1.25v or
1.35v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		 154 million
0.09µm process
183mm² die
Athlon 64 X2 4000+ MMX 3DNow! SSE SSE2 SSE3
(Windsor)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
(dual core)
May 23, 2006 - {$328}		 940 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.25v or 1.35v or
1.4v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Athlon 64 X2 4200+ MMX 3DNow! SSE SSE2 SSE3
(Windsor)
(128-bit on-Die unbuffered DDR2 PC5800 mem controller; 8GB max)
(dual core)
May 23, 2006 - {$365}		 940 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.25v or 1.35v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		 154 million
0.09µm process
183mm² die
Athlon 64 X2 4400+ MMX 3DNow! SSE SSE2 SSE3
(Windsor)
(128-bit on-Die unbuffered DDR2 PC5800 mem controller; 8GB max)
(dual core)
May 23, 2006 - {$470}		 940 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.25v or 1.35v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Athlon 64 X2 4600+ MMX 3DNow! SSE SSE2 SSE3
(Windsor)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
(dual core)
May 23, 2006 - {$558}		 940 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.25v or 1.35v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		 154 million
0.09µm process
183mm² die
Athlon 64 X2 4800+ MMX 3DNow! SSE SSE2 SSE3
(Windsor)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
(dual core)
May 23, 2006 - {$645}		 940 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.25v or 1.35v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Athlon 64 X2 5000+ MMX 3DNow! SSE SSE2 SSE3
(Windsor)
(128-bit on-Die unbuffered DDR2 PC5800 mem controller; 8GB max)
(dual core)
May 23, 2006 - {$696}		 940 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
1.25v or 1.35v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		 154 million
0.09µm process
183mm² die
Athlon 64 X2 5200+ MMX 3DNow! SSE SSE2 SSE3
(Windsor)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller)
(dual core)
December 12, 2006 - {$403}		 940 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
1.25v or 1.35v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Athlon 64 X2 5400+ MMX 3DNow! SSE SSE2 SSE3
(Windsor)
(128-bit on-Die unbuffered DDR2 PC5800 mem controller; 8GB max)
(dual core)
December 12, 2006 - {$485}		 940 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
1.35v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		 154 million
0.09µm process
183mm² die
Athlon 64 X2 5600+ MMX 3DNow! SSE SSE2 SSE3
(Windsor)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller)
(dual core)
December 12, 2006 - {$505}		 940 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
1.35v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Athlon 64 X2 6000+ MMX 3DNow! SSE SSE2 SSE3
(Windsor)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller)
(dual core)
February 20, 2007 - {$464}		 940 pins
3000MHz (200x15)
(64-bit dual-pumped bus)
1.4v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Athlon 64 X2 6400+ MMX 3DNow! SSE SSE2 SSE3
(Windsor)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller)
(dual core)
2007		 940 pins
3200MHz (200x16)
(64-bit dual-pumped bus)
1.4v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die

Athlon X2 BE 2300 MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
(dual core)
June 7, 2007 - {$86}		 940 pins
1900MHz (200x9.5)
(64-bit dual-pumped bus)
1.25v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		 154 million
0.065µm process
126mm² die
Athlon X2 BE 2350 MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
(dual core)
June 7, 2007 - {$91}		 940 pins
2100MHz (200x10.5)
(64-bit dual-pumped bus)
1.25v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		 154 million
0.065µm process
126mm² die
Athlon X2 BE 2400 MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
(dual core)
2007 - {$104}		 940 pins
2300MHz (200x11.5)
(64-bit dual-pumped bus)
1.25v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		 154 million
0.065µm process
126mm² die
Athlon 64 X2 3600+ MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
(dual core)
March, 2007 - {$102}		 940 pins
1900MHz (200x9.5)
(64-bit dual-pumped bus)
1.35v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		 154 million
0.065µm process
126mm² die
Athlon 64 X2 4000+ MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
(dual core)
December 5, 2006		 940 pins
2100MHz (200x10.5)
(64-bit dual-pumped bus)
1.35v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		 154 million
0.065µm process
126mm² die
Athlon 64 X2 4050e MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
(dual core)
2Q 2008		 940 pins
2100MHz (200x10.5)
(64-bit dual-pumped bus)
1.25v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		 154 million
0.065µm process
126mm² die
Athlon 64 X2 4200+ MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
(dual core)
2007		 940 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.325v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		 154 million
0.065µm process
126mm² die
Athlon 64 X2 4400+ MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
(dual core)
December 5, 2006
2007 - 1.375v		 940 pins
2300MHz (200x11.5)
(64-bit dual-pumped bus)
1.35v, 1.375v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		 154 million
0.065µm process
126mm² die
Athlon 64 X2 4450e MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
(dual core)
2Q 2008		 940 pins
2300MHz (200x11.5)
(64-bit dual-pumped bus)
1.25v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		 154 million
0.065µm process
126mm² die
Athlon 64 X2 4600+ MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
(dual core)
2008		 940 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.375v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		 154 million
0.065µm process
126mm² die
Athlon 64 X2 4800+ MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
(dual core)
December 5, 2006		 940 pins
2500MHz (200x12.5)
(64-bit dual-pumped bus)
1.35v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		 154 million
0.065µm process
126mm² die
Athlon 64 X2 4850e MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
(dual core)
April 3, 2008		 940 pins
2500MHz (200x12.5)
(64-bit dual-pumped bus)
1.25v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		 154 million
0.065µm process
126mm² die
Athlon 64 X2 5000+ MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
(dual core)
December 5, 2006		 940 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
1.35v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		 154 million
0.065µm process
126mm² die
Athlon 64 X2 5200+ MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
(dual core)
2007		 940 pins
2700MHz (200x13.5)
(64-bit dual-pumped bus)
1.375v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		 154 million
0.065µm process
126mm² die
Athlon 64 X2 5400+ MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
(dual core)
[not released]		 940 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
1.35v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		 154 million
0.065µm process
126mm² die
Athlon 64 X2 6000+ MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
(dual core)
1H 2008		 940 pins
3100MHz (200x15.5)
(64-bit dual-pumped bus)
1.4v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		 154 million
0.065µm process
126mm² die

Athlon 64 X2 ??? MMX 3DNow! SSE SSE2 SSE3 SSE4
(Rana)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller)
(dual core, HT 3.0, DICE)
2008?		 940 pins
?MHz (200x?)
(64-bit dual-pumped bus)
?v		 Socket AM2+ 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		 ? million
0.065µm process
?mm² die
AMD
Processors		 Natural
State		 Sockets L1/L2/L3 Cache
(Associativity)		 Transistors
Phenom 9500 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Agena)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller)
(quad core, HT 3.0, DICE)
November 19, 2007 - {$251}		 940 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.25v		 Socket AM2+ 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die
Phenom 9600 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Agena)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller)
(quad core, HT 3.0, DICE)
November 19, 2007 - {$283}		 940 pins
2300MHz (200x11.5)
(64-bit dual-pumped bus)
1.25v		 Socket AM2+ 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die
Phenom 9700 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Agena)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller)
(quad core, HT 3.0, DICE)
[not released]		 940 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
?v		 Socket AM2+ 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die
Phenom 9900 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Agena)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller)
(quad core, HT 3.0, DICE)
[not released]		 940 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
?v		 Socket AM2+ 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die

Phenom X2 ??? MMX 3DNow! SSE SSE2 SSE3 SSE4
(Regor)
(128-bit on-Die unbuffered DDR3 PC? mem controller)
(dual core, HT 3.0, DICE)
2009?		 ? pins
?MHz (200x?)
(64-bit dual-pumped bus)
?v		 Socket AM3 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		 ? million
0.045µm process
?mm² die

Phenom X2 6??? MMX 3DNow! SSE SSE2 SSE3 SSE4
(Kuma)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller)
(dual core, HT 3.0, DICE)
2008?		 940 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
?v		 Socket AM2+ 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 ? million
0.065µm process
?mm² die
Phenom X2 6??? MMX 3DNow! SSE SSE2 SSE3 SSE4
(Kuma)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller)
(dual core, HT 3.0, DICE)
2008?		 940 pins
?MHz (200x?)
(64-bit dual-pumped bus)
?v		 Socket AM2+ 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 ? million
0.065µm process
?mm² die

Phenom X2 6??? MMX 3DNow! SSE SSE2 SSE3 SSE4
(Propus)
(128-bit on-Die unbuffered DDR3 PC? mem controller)
(dual core, HT 3.0, DICE)
2009?		 ? pins
?MHz (200x?)
(64-bit dual-pumped bus)
?v		 Socket AM3 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 ? million
0.045µm process
?mm² die

Phenom X3 8250e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Toliman)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller)
(tri core, HT 3.0, DICE)
August 2008?		 940 pins
1900MHz (200x9.5)
(64-bit dual-pumped bus)
1.25v		 Socket AM2+ 3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die
Phenom X3 8400 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Toliman)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller)
(tri core, HT 3.0, DICE)
March 27, 2008		 940 pins
2100MHz (200x10.5)
(64-bit dual-pumped bus)
1.25v		 Socket AM2+ 3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die
Phenom X3 8450e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Toliman)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller)
(tri core, HT 3.0, DICE)
August 2008?		 940 pins
2100MHz (200x10.5)
(64-bit dual-pumped bus)
1.25v		 Socket AM2+ 3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die
Phenom X3 8450 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Toliman)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller)
(tri core, HT 3.0, DICE)
April 23, 2008 - {$145}		 940 pins
2100MHz (200x10.5)
(64-bit dual-pumped bus)
1.25v		 Socket AM2+ 3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die
Phenom X3 8600 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Toliman)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller)
(tri core, HT 3.0, DICE)
March 27, 2008		 940 pins
2300MHz (200x11.5)
(64-bit dual-pumped bus)
1.25v		 Socket AM2+ 3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die
Phenom X3 8650 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Toliman)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller)
(tri core, HT 3.0, DICE)
April 23, 2008 - {$165}		 940 pins
2300MHz (200x11.5)
(64-bit dual-pumped bus)
1.25v		 Socket AM2+ 3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die
Phenom X3 8750 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Toliman)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller)
(tri core, HT 3.0, DICE)
April 23, 2008 - {$195}		 940 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.25v		 Socket AM2+ 3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die
Phenom X3 8??? MMX 3DNow! SSE SSE2 SSE3 SSE4
(Toliman)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller)
(tri core, HT 3.0, DICE)
2008?		 940 pins
?MHz (200x?)
(64-bit dual-pumped bus)
?v		 Socket AM2+ 3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die

Phenom X3 ??? MMX 3DNow! SSE SSE2 SSE3 SSE4
(Heka)
(128-bit on-Die unbuffered DDR3 PC? mem controller)
(tri core, HT 3.0, DICE)
2009?		 ? pins
?MHz (200x?)
(64-bit dual-pumped bus)
?v		 Socket AM3 3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)
?MB on-Die shared L3 (32-way)		 ? million
0.045µm process
?mm² die

Phenom X4 9100e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Agena)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller)
(quad core, HT 3.0, DICE)
March 27, 2008		 940 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
1.15v		 Socket AM2+ 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die
Phenom X4 9150e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Agena)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller)
(quad core, HT 3.0, DICE)
July 1, 2008 - {$175}		 940 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
1.125v		 Socket AM2+ 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die
Phenom X4 9350e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Agena)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller)
(quad core, HT 3.0, DICE)
July 1, 2008 - {$195}		 940 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.125v		 Socket AM2+ 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die
Phenom X4 9550 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Agena)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller)
(quad core, HT 3.0, DICE)
March 27, 2008 - {$209}		 940 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.25v		 Socket AM2+ 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die
Phenom X4 9650 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Agena)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller)
(quad core, HT 3.0, DICE)
March 27, 2008 - {$215}		 940 pins
2300MHz (200x11.5)
(64-bit dual-pumped bus)
1.25v		 Socket AM2+ 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die
Phenom X4 9750 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Agena)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller)
(quad core, HT 3.0, DICE)
March 27, 2008 - {$215}		 940 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.25v or 1.3v		 Socket AM2+ 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die
Phenom X4 9850 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Agena)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller)
(quad core, HT 3.0, DICE)
March 27, 2008 - {$235}		 940 pins
2500MHz (200x12.5)
(64-bit dual-pumped bus)
1.25v		 Socket AM2+ 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die
Phenom X4 9950 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Agena)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller)
(quad core, HT 3.0, DICE)
July 1, 2008 - {$235}		 940 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
1.3v		 Socket AM2+ 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die
Phenom X4 9??? MMX 3DNow! SSE SSE2 SSE3 SSE4
(Agena)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller)
(quad core, HT 3.0, DICE)
2008?		 940 pins
?MHz (200x?)
(64-bit dual-pumped bus)
?v		 Socket AM2+ 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die

Phenom X4 9??? MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC? mem controller)
(quad core, HT 3.0, DICE)
4Q 2008?		 ? pins
2400MHz (200x12)
(64-bit dual-pumped bus)
?v		 Socket AM3 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
?MB on-Die shared L3 (32-way)		 ? million
0.045µm process
?mm² die
Phenom X4 9??? MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC? mem controller)
(quad core, HT 3.0, DICE)
4Q 2008?		 ? pins
2800MHz (200x14)
(64-bit dual-pumped bus)
?v		 Socket AM3 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
?MB on-Die shared L3 (32-way)		 ? million
0.045µm process
?mm² die
Phenom X4 9??? MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC? mem controller)
(quad core, HT 3.0, DICE)
2009?		 ? pins
?MHz (200x?)
(64-bit dual-pumped bus)
?v		 Socket AM3 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
?MB on-Die shared L3 (32-way)		 ? million
0.045µm process
?mm² die

Phenom X4 9??? MMX 3DNow! SSE SSE2 SSE3 SSE4
(Ridgeback)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller)
(quad core, HT 3.0, DICE)
2008?		 940 pins
?MHz (200x?)
(64-bit dual-pumped bus)
?v		 Socket AM2+ 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		 ? million
0.045µm process
243mm² die
AMD
Processors		 Natural
State		 Sockets L1/L2 Cache
(Associativity)		 Transistors
Sempron 2800+ MMX 3DNow! SSE SSE2 SSE3
(Manila)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
May 23, 2006		 940 pins
1600MHz (200x8)
(64-bit dual-pumped bus)
1.4v		 Socket AM2
Socket AM2+		 64KB data (2-way)
64KB instruction (2-way)
128KB on-Die unified L2 (16-way exclusive)		 81 million
0.09µm process
103mm² die
Sempron 3000+ MMX 3DNow! SSE SSE2 SSE3
(Manila)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
May 23, 2006 - {$77}		 940 pins
1600MHz (200x8)
(64-bit dual-pumped bus)
1.25v or 1.4v		 Socket AM2
Socket AM2+		 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)		 81 million
0.09µm process
103mm² die
Sempron 3200+ MMX 3DNow! SSE SSE2 SSE3
(Manila)
(128-bit on-Die unbuffered DDR2 PC5800 mem controller; 8GB max)
May 23, 2006 - {$87}		 940 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
1.25v or 1.4v		 Socket AM2
Socket AM2+		 64KB data (2-way)
64KB instruction (2-way)
128KB on-Die unified L2 (16-way exclusive)		 81 million
0.09µm process
103mm² die
Sempron 3400+ MMX 3DNow! SSE SSE2 SSE3
(Manila)
(128-bit on-Die unbuffered DDR2 PC5800 mem controller; 8GB max)
May 23, 2006 - {$97}		 940 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
1.25v or 1.4v		 Socket AM2
Socket AM2+		 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)		 81 million
0.09µm process
103mm² die
Sempron 3500+ MMX 3DNow! SSE SSE2 SSE3
(Manila)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
May 23, 2006 - {$109}		 940 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.25v or 1.4v		 Socket AM2
Socket AM2+		 64KB data (2-way)
64KB instruction (2-way)
128KB on-Die unified L2 (16-way exclusive)		 81 million
0.09µm process
103mm² die
Sempron 3600+ MMX 3DNow! SSE SSE2 SSE3
(Manila)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
May 23, 2006 - {$123}		 940 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.4v		 Socket AM2
Socket AM2+		 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)		 81 million
0.09µm process
103mm² die
Sempron 3800+ MMX 3DNow! SSE SSE2 SSE3
(Manila)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
2007? - {$108}		 940 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.4v		 Socket AM2
Socket AM2+		 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)		 81 million
0.09µm process
103mm² die

Sempron LE 1100 MMX 3DNow! SSE SSE2 SSE3
(Sparta)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
4Q 2007 - {$37}		 940 pins
1900MHz (200x9.5)
(64-bit dual-pumped bus)
1.4v		 Socket AM2
Socket AM2+		 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)		 81 million
0.065µm process
?mm² die
Sempron LE 1150 MMX 3DNow! SSE SSE2 SSE3
(Sparta)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
4Q 2007 - {$42}		 940 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.4v		 Socket AM2
Socket AM2+		 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)		 81 million
0.065µm process
?mm² die
Sempron LE 1200 MMX 3DNow! SSE SSE2 SSE3
(Sparta)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
4Q 2007 - {$48}		 940 pins
2100MHz (200x10.5)
(64-bit dual-pumped bus)
1.4v		 Socket AM2
Socket AM2+		 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		 81 million
0.065µm process
?mm² die
Sempron LE 1250 MMX 3DNow! SSE SSE2 SSE3
(Sparta)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
4Q 2007 - {$53}		 940 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.4v		 Socket AM2
Socket AM2+		 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		 81 million
0.065µm process
?mm² die
Sempron LE 1300 MMX 3DNow! SSE SSE2 SSE3
(Sparta)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
2008 - {$41}		 940 pins
2300MHz (200x11.5)
(64-bit dual-pumped bus)
1.4v		 Socket AM2
Socket AM2+		 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		 81 million
0.065µm process
?mm² die

Sempron ??? MMX 3DNow! SSE SSE2 SSE3 SSE4
(Spica)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller)
(HT 3.0, DICE)
2008?		 940 pins
?MHz (200x?)
(64-bit dual-pumped bus)
?v		 Socket AM2+ 64KB data (2-way)
64KB instruction (2-way)
?KB on-Die unified L2 (16-way exclusive)		 ? million
0.065µm process
?mm² die

Sempron ??? MMX 3DNow! SSE SSE2 SSE3 SSE4
(Sargas)
(128-bit on-Die unbuffered DDR3 PC? mem controller)
(HT 3.0, DICE)
2009?		 ? pins
?MHz (200x?)
(64-bit dual-pumped bus)
?v		 Socket AM3 64KB data (2-way)
64KB instruction (2-way)
?KB on-Die unified L2 (16-way exclusive)		 ? million
0.045µm process
?mm² die


Business-Class Athlon / Phenom
AMD
Processors		 Natural
State		 Sockets L1/L2/L3 Cache
(Associativity)		 Transistors
Athlon 1640B MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
April 28, 2008 - {$50}		 940 pins
2700MHz (200x13.5)
(64-bit dual-pumped bus)
1.4v		 Socket AM2
Socket AM2+		 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		 154 million
0.065µm process
126mm² die

Athlon X2 4450B MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
(dual core)
April 28, 2008 - {$85}		 940 pins
2300MHz (200x11.5)
(64-bit dual-pumped bus)
1.25v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		 154 million
0.065µm process
126mm² die
Athlon X2 5000B MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
(dual core)
April 28, 2008 - {$95}		 940 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
1.375v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		 154 million
0.065µm process
126mm² die
Athlon X2 5200B MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
(dual core)
April 28, 2008 - {$110}		 940 pins
2700MHz (200x13.5)
(64-bit dual-pumped bus)
1.375v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		 154 million
0.065µm process
126mm² die
Athlon X2 5400B MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
(dual core)
April 28, 2008 - {$120}		 940 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
1.35v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		 154 million
0.065µm process
126mm² die

Phenom X3 8600B MMX 3DNow! SSE SSE2 SSE3 SSE4
(Toliman)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller)
(tri core, HT 3.0, DICE)
April 28, 2008 - {$175}		 940 pins
2300MHz (200x11.5)
(64-bit dual-pumped bus)
1.25v		 Socket AM2+ 3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (?-way)		 463 million
0.065µm process
288mm² die

Phenom X4 9600B MMX 3DNow! SSE SSE2 SSE3 SSE4
(Agena)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller)
(quad core, HT 3.0, DICE)
April 28, 2008 - {$230}		 940 pins
2300MHz (200x11.5)
(64-bit dual-pumped bus)
1.25v		 Socket AM2+ 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (?-way)		 463 million
0.065µm process
288mm² die


Athlon 64 FX
AMD
Processors		 Natural
State		 Sockets L1/L2/L3 Cache
(Associativity)		 Transistors
Athlon 64 FX-51 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
September 23, 2003 - {$733}		 940 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.5v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 106 million
0.13µm process
193mm² die
Athlon 64 FX-53 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
March 18, 2004 - {$733}		 940 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.5v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 106 million
0.13µm process
193mm² die

Athlon 64 FX-53 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max)
June 1, 2004 - {$799}		 939 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.5v		 Socket 939 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 106 million
0.13µm process
193mm² die
Athlon 64 FX-55 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max)
October 19, 2004 - {$827}		 939 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
1.5v		 Socket 939 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 106 million
0.13µm process
193mm² die

Athlon 64 FX-57 MMX 3DNow! SSE SSE2 SSE3
(San Diego)
(128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max)
June 27, 2005 - {$1031}		 939 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
1.4v		 Socket 939 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 114 million
0.09µm process
115mm² die

Athlon 64 FX-62 MMX 3DNow! SSE SSE2 SSE3
(Toledo)
(128-bit on-Die unbuffered DDR mem controller)
(dual core)
May 23, 2006 - {$1031}		 940 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
1.4v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 233 million
0.09µm process
~199mm² die

Athlon 64 FX-60 MMX 3DNow! SSE SSE2 SSE3
(Toledo)
(128-bit on-Die unbuffered DDR mem controller)
(dual core)
January 10, 2006 - {$1031}		 939 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
1.35v		 Socket 939 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 233 million
0.09µm process
~199mm² die
Athlon 64 FX-62 MMX 3DNow! SSE SSE2 SSE3
(Toledo)
(128-bit on-Die unbuffered DDR mem controller)
(dual core)
May 23, 2006 - {$1031}		 939 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
1.4v		 Socket 939 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 233 million
0.09µm process
~199mm² die

Athlon 64 FX-70 MMX 3DNow! SSE SSE2 SSE3
(Windsor)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller)
(dual core)
November 30, 2006 - {$599}		 1207 balls
2600MHz (200x13)
(64-bit dual-pumped bus)
1.4v		 Socket F 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Athlon 64 FX-72 MMX 3DNow! SSE SSE2 SSE3
(Windsor)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller)
(dual core)
November 30, 2006 - {$799}		 1207 balls
2800MHz (200x14)
(64-bit dual-pumped bus)
1.4v		 Socket F 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Athlon 64 FX-74 MMX 3DNow! SSE SSE2 SSE3
(Windsor)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller)
(dual core)
November 30, 2006 - {$999}		 1207 balls
3000MHz (200x15)
(64-bit dual-pumped bus)
1.4v		 Socket F 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Athlon 64 FX-76 MMX 3DNow! SSE SSE2 SSE3
(Windsor)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller)
(dual core)
[not released]		 1207 balls
3200MHz (200x16)
(64-bit dual-pumped bus)
1.4v		 Socket F 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die

Phenom FX-80 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Agena FX)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller)
(quad core, HT 3.0, DICE)
2008?		 1207 balls
2200MHz (200x11)
(64-bit dual-pumped bus)
?v		 Socket F+ 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die
Phenom FX-??? MMX 3DNow! SSE SSE2 SSE3 SSE4
(Agena FX)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller)
(quad core, HT 3.0, DICE)
2008?		 1207 balls
?MHz (200x?)
(64-bit dual-pumped bus)
?v		 Socket F+ 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die

Phenom FX-??? MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb FX)
(128-bit on-Die unbuffered DDR3 PC? mem controller)
(quad core, HT 3.0, DICE)
2009?		 ? pins
?MHz (200x?)
(64-bit dual-pumped bus)
?v		 Socket AM3 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
?MB on-Die shared L3 (32-way)		 ? million
0.045µm process
?mm² die


APUs
AMD
Processors		 Natural
State		 Sockets L1/L2/L3 Cache
(Associativity)		 Transistors
???
("Stars"-family)
(128-bit on-Die unbuffered DDR3 PC? mem controller)
(? core)
2009?		 ? balls
?MHz (?x?)
(64-bit dual-pumped bus)
?v		 Socket FS1 ?x ?KB data (?-way)
?x ?KB instruction (?-way)
?x ?KB on-Die unified L2 (?-way exclusive)
?MB on-Die shared L3 (?-way)		 ? million
0.045µm process
?mm² die


AMD Server


Opteron (Socket 940)
(NOT compatible with Socket AM2 CPUs!)
AMD
Processors		 Natural
State		 Sockets L1/L2 Cache
(Associativity)		 Transistors
Opteron ??? MMX 3DNow! SSE SSE2
(Clawhammer DP)
(128-bit on-Die DDR PC2700 mem controller; 8GB max)
[not released]		 940 pins
?MHz (200x?)
(64-bit dual-pumped bus)
?v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		 ? million
0.13µm process
104mm² die

Opteron 140 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC2700 mem controller; 8GB max)
June 30, 2003 - {$229}		 940 pins
1400MHz (200x7)
(64-bit dual-pumped bus)
1.5v or 1.55v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 106 million
0.13µm process
193mm² die
Opteron 140EE MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC2700 mem controller; 8GB max)
January, 2005		 940 pins
1400MHz (200x7)
(64-bit dual-pumped bus)
1.15v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 106 million
0.13µm process
193mm² die
Opteron 142 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC2700 mem controller; 8GB max)
June 30, 2003 - {$438}		 940 pins
1600MHz (200x8)
(64-bit dual-pumped bus)
1.5v or 1.55v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 106 million
0.13µm process
193mm² die
Opteron 144 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC2700 mem controller; 8GB max)
June 30, 2003 - {$669}		 940 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
1.5v or 1.55v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 106 million
0.13µm process
193mm² die
Opteron 146 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
September 9, 2003 - {$669}		 940 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.5v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 106 million
0.13µm process
193mm² die
Opteron 146HE MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
2005?		 940 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
?v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 106 million
0.13µm process
193mm² die
Opteron 148 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
November 17, 2003 - {$733}		 940 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.5v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 106 million
0.13µm process
193mm² die
Opteron 150 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
May 18, 2004 - {$637}		 940 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.5v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 106 million
0.13µm process
193mm² die
Opteron 240 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC2700 mem controller; 8GB max)
April 22, 2003 - {$283}		 940 pins
1400MHz (200x7)
(64-bit dual-pumped bus)
1.5v or 1.55v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 106 million
0.13µm process
193mm² die
Opteron 240EE MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
January, 2005		 940 pins
1400MHz (200x7)
(64-bit dual-pumped bus)
1.15v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 106 million
0.13µm process
193mm² die
Opteron 242 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC2700 mem controller; 8GB max)
April 22, 2003 - {$690}		 940 pins
1600MHz (200x8)
(64-bit dual-pumped bus)
1.5v or 1.55v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 106 million
0.13µm process
193mm² die
Opteron 244 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC2700 mem controller; 8GB max)
April 22, 2003 - {$794}		 940 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
1.5v or 1.55v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 106 million
0.13µm process
193mm² die
Opteron 246 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
August 5, 2003 - {$794}		 940 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.5v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 106 million
0.13µm process
193mm² die
Opteron 246HE MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
January, 2005		 940 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
?v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 106 million
0.13µm process
193mm² die
Opteron 248 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
November 17, 2003 - {$913}		 940 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.5v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 106 million
0.13µm process
193mm² die
Opteron 250 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
May 18, 2004 - {$851}		 940 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.5v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 106 million
0.13µm process
193mm² die
Opteron 840 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC2700 mem controller; 8GB max)
June 30, 2003 - {$749}		 940 pins
1400MHz (200x7)
(64-bit dual-pumped bus)
1.5v or 1.55v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 106 million
0.13µm process
193mm² die
Opteron 840EE MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
January, 2005		 940 pins
1400MHz (200x7)
(64-bit dual-pumped bus)
1.15v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 106 million
0.13µm process
193mm² die
Opteron 842 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC2700 mem controller; 8GB max)
June 30, 2003 - {$1299}		 940 pins
1600MHz (200x8)
(64-bit dual-pumped bus)
1.5v or 1.55v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 106 million
0.13µm process
193mm² die
Opteron 844 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC2700 mem controller; 8GB max)
June 30, 2003 - {$2149}		 940 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
1.5v or 1.55v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 106 million
0.13µm process
193mm² die
Opteron 846 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
September 9, 2003 - {$3199}		 940 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.5v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 106 million
0.13µm process
193mm² die
Opteron 846HE MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
2005?		 940 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
?v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 106 million
0.13µm process
193mm² die
Opteron 848 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
November 17, 2003 - {$3199}		 940 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.5v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 106 million
0.13µm process
193mm² die
Opteron 850 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
May 18, 2004 - {$1514}		 940 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.5v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 106 million
0.13µm process
193mm² die

Opteron 146 MMX 3DNow! SSE SSE2
(Venus)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
February 14, 2005		 940 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.4v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 114 million
0.09µm process
115mm² die
Opteron 148HE MMX 3DNow! SSE SSE2
(Venus)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
1Q 2005		 940 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.3v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 114 million
0.09µm process
115mm² die
Opteron 152 MMX 3DNow! SSE SSE2
(Venus)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
2006		 940 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
?v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 114 million
0.09µm process
115mm² die
Opteron 154 MMX 3DNow! SSE SSE2
(Venus)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
2006		 940 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
?v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 114 million
0.09µm process
115mm² die
Opteron 156 MMX 3DNow! SSE SSE2
(Venus)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
2006		 940 pins
3000MHz (200x15)
(64-bit dual-pumped bus)
?v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 114 million
0.09µm process
115mm² die

Opteron 242 MMX 3DNow! SSE SSE2 SSE3
(Troy)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
February 14, 2005 - {$163}		 940 pins
1600MHz (200x8)
(64-bit dual-pumped bus)
1.35v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 114 million
0.09µm process
115mm² die
Opteron 244 MMX 3DNow! SSE SSE2 SSE3
(Troy)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
February 14, 2005 - {$209}		 940 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
1.35v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 114 million
0.09µm process
115mm² die
Opteron 246 MMX 3DNow! SSE SSE2 SSE3
(Troy)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
February 14, 2005 - {$316}		 940 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.35v or 1.4v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 114 million
0.09µm process
115mm² die
Opteron 248 MMX 3DNow! SSE SSE2 SSE3
(Troy)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
February 14, 2005 - {$455}		 940 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.35v or 1.4v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 114 million
0.09µm process
115mm² die
Opteron 248HE MMX 3DNow! SSE SSE2 SSE3
(Troy)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
1Q 2005		 940 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.3v or 1.4v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 114 million
0.09µm process
115mm² die
Opteron 250 MMX 3DNow! SSE SSE2 SSE3
(Troy)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
February 14, 2005 - {$690}		 940 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.35v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 114 million
0.09µm process
115mm² die
Opteron 252 MMX 3DNow! SSE SSE2 SSE3
(Troy)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
February 14, 2005 - {$851}		 940 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
1.35v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 114 million
0.09µm process
115mm² die
Opteron 254 MMX 3DNow! SSE SSE2 SSE3
(Troy)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
October, 2005 - {$851}		 940 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
1.35v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 114 million
0.09µm process
115mm² die
Opteron 256 MMX 3DNow! SSE SSE2 SSE3
(Troy)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
2006		 940 pins
3000MHz (200x15)
(64-bit dual-pumped bus)
1.35v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 114 million
0.09µm process
115mm² die

Opteron 842 MMX 3DNow! SSE SSE2 SSE3
(Athens)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
February 14, 2005 - {$698}		 940 pins
1600MHz (200x8)
(64-bit dual-pumped bus)
1.35v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 114 million
0.09µm process
115mm² die
Opteron 844 MMX 3DNow! SSE SSE2 SSE3
(Athens)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
February 14, 2005 - {$698}		 940 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
1.35v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 114 million
0.09µm process
115mm² die
Opteron 846 MMX 3DNow! SSE SSE2 SSE3
(Athens)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
February 14, 2005 - {$698}		 940 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.35v or 1.4v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 114 million
0.09µm process
115mm² die
Opteron 848 MMX 3DNow! SSE SSE2 SSE3
(Athens)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
February 14, 2005 - {$873}		 940 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.35v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 114 million
0.09µm process
115mm² die
Opteron 848HE MMX 3DNow! SSE SSE2 SSE3
(Athens)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
1Q 2005		 940 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.3v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 114 million
0.09µm process
115mm² die
Opteron 850 MMX 3DNow! SSE SSE2 SSE3
(Athens)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
February 14, 2005 - {$1165}		 940 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.35v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 114 million
0.09µm process
115mm² die
Opteron 852 MMX 3DNow! SSE SSE2 SSE3
(Athens)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
February 14, 2005 - {$1514}		 940 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
1.35v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 114 million
0.09µm process
115mm² die
Opteron 854 MMX 3DNow! SSE SSE2 SSE3
(Athens)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
August, 2005		 940 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
1.35v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 114 million
0.09µm process
115mm² die
Opteron 856 MMX 3DNow! SSE SSE2 SSE3
(Athens)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
2006		 940 pins
3000MHz (200x15)
(64-bit dual-pumped bus)
1.35v		 Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 114 million
0.09µm process
115mm² die

Opteron 165 MMX 3DNow! SSE SSE2 SSE3
(Denmark)
(128-bit on-Die registered DDR PC3200 mem controller)
(dual core)
August 24, 2005 - {$637}		 940 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
?v		 Socket 940 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 233 million
0.09µm process
199mm² die
Opteron 165EE MMX 3DNow! SSE SSE2 SSE3
(Denmark)
(128-bit on-Die registered DDR PC3200 mem controller)
(dual core)
2H 2005		 940 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
1.15v		 Socket 940 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 233 million
0.09µm process
199mm² die
Opteron 170 MMX 3DNow! SSE SSE2 SSE3
(Denmark)
(128-bit on-Die registered DDR PC3200 mem controller)
(dual core)
August 24, 2005 - {$799}		 940 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
?v		 Socket 940 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 233 million
0.09µm process
199mm² die
Opteron 175 MMX 3DNow! SSE SSE2 SSE3
(Denmark)
(128-bit on-Die registered DDR PC3200 mem controller)
(dual core)
August 24, 2005 - {$999}		 940 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
?v		 Socket 940 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 233 million
0.09µm process
199mm² die
Opteron 180 MMX 3DNow! SSE SSE2 SSE3
(Denmark)
(128-bit on-Die registered DDR PC3200 mem controller)
(dual core)
October 24, 2005 - {$799}		 940 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
?v		 Socket 940 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 233 million
0.09µm process
199mm² die
Opteron 185 MMX 3DNow! SSE SSE2 SSE3
(Denmark)
(128-bit on-Die registered DDR PC3200 mem controller)
(dual core)
April, 2006? - {$}		 940 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
?v		 Socket 940 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 233 million
0.09µm process
199mm² die

Opteron 260HE MMX 3DNow! SSE SSE2 SSE3
(Italy)
(128-bit on-Die registered DDR PC3200 mem controller)
(dual core)
2H 2005		 940 pins
1600MHz (200x8)
(64-bit dual-pumped bus)
1.15v		 Socket 940 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 233 million
0.09µm process
199mm² die
Opteron 265 MMX 3DNow! SSE SSE2 SSE3
(Italy)
(128-bit on-Die registered DDR PC3200 mem controller)
(dual core)
August 4, 2005 - {$851}		 940 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
1.35v		 Socket 940 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 233 million
0.09µm process
199mm² die
Opteron 265HE MMX 3DNow! SSE SSE2 SSE3
(Italy)
(128-bit on-Die registered DDR PC3200 mem controller)
(dual core)
2H 2005		 940 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
1.15v		 Socket 940 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 233 million
0.09µm process
199mm² die
Opteron 270 MMX 3DNow! SSE SSE2 SSE3
(Italy)
(128-bit on-Die registered DDR PC3200 mem controller)
(dual core)
August 4, 2005 - {$1051}		 940 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.35v		 Socket 940 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 233 million
0.09µm process
199mm² die
Opteron 270HE MMX 3DNow! SSE SSE2 SSE3
(Italy)
(128-bit on-Die registered DDR PC3200 mem controller)
(dual core)
2H 2005		 940 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.15v		 Socket 940 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 233 million
0.09µm process
199mm² die
Opteron 275 MMX 3DNow! SSE SSE2 SSE3
(Italy)
(128-bit on-Die registered DDR PC3200 mem controller)
(dual core)
August 4, 2005 - {$1299}		 940 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.35v		 Socket 940 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 233 million
0.09µm process
199mm² die
Opteron 275HE MMX 3DNow! SSE SSE2 SSE3
(Italy)
(128-bit on-Die registered DDR PC3200 mem controller)
(dual core)
2006		 940 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.15v		 Socket 940 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 233 million
0.09µm process
199mm² die
Opteron 280 MMX 3DNow! SSE SSE2 SSE3
(Italy)
(128-bit on-Die registered DDR PC3200 mem controller)
(dual core)
September 26, 2005 - {$1299}		 940 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.35v		 Socket 940 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 233 million
0.09µm process
199mm² die
Opteron 285 MMX 3DNow! SSE SSE2 SSE3
(Italy)
(128-bit on-Die registered DDR PC3200 mem controller)
(dual core)
March 6, 2006 - {$1051}		 940 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
1.35v		 Socket 940 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 233 million
0.09µm process
199mm² die
Opteron 290 MMX 3DNow! SSE SSE2 SSE3
(Italy)
(128-bit on-Die registered DDR PC3200 mem controller)
(dual core)
2006		 940 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
1.35v		 Socket 940 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 233 million
0.09µm process
199mm² die

Opteron 860HE MMX 3DNow! SSE SSE2 SSE3
(Egypt)
(128-bit on-Die registered DDR PC3200 mem controller)
(dual core)
2H 2005		 940 pins
1600MHz (200x8)
(64-bit dual-pumped bus)
1.2v		 Socket 940 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 233 million
0.09µm process
199mm² die
Opteron 865 MMX 3DNow! SSE SSE2 SSE3
(Egypt)
(128-bit on-Die registered DDR PC3200 mem controller)
(dual core)
April 21, 2005 - {$1514}		 940 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
?v		 Socket 940 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 233 million
0.09µm process
199mm² die
Opteron 865HE MMX 3DNow! SSE SSE2 SSE3
(Egypt)
(128-bit on-Die registered DDR PC3200 mem controller)
(dual core)
2H 2005		 940 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
1.2v		 Socket 940 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 233 million
0.09µm process
199mm² die
Opteron 870 MMX 3DNow! SSE SSE2 SSE3
(Egypt)
(128-bit on-Die registered DDR PC3200 mem controller)
(dual core)
April 21, 2005 - {$2169}		 940 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
?v		 Socket 940 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 233 million
0.09µm process
199mm² die
Opteron 870HE MMX 3DNow! SSE SSE2 SSE3
(Egypt)
(128-bit on-Die registered DDR PC3200 mem controller)
(dual core)
2H 2005		 940 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.2v		 Socket 940 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 233 million
0.09µm process
199mm² die
Opteron 875 MMX 3DNow! SSE SSE2 SSE3
(Egypt)
(128-bit on-Die registered DDR PC3200 mem controller)
(dual core)
April 21, 2005 - {$2649}		 940 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
?v		 Socket 940 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 233 million
0.09µm process
199mm² die
Opteron 880 MMX 3DNow! SSE SSE2 SSE3
(Egypt)
(128-bit on-Die registered DDR PC3200 mem controller)
(dual core)
September 26, 2005 - {$2649}		 940 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
?v		 Socket 940 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 233 million
0.09µm process
199mm² die
Opteron 885 MMX 3DNow! SSE SSE2 SSE3
(Egypt)
(128-bit on-Die registered DDR PC3200 mem controller)
(dual core)
March 6, 2006 - {$2149}		 940 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
?v		 Socket 940 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 233 million
0.09µm process
199mm² die
Opteron 890 MMX 3DNow! SSE SSE2 SSE3
(Egypt)
(128-bit on-Die registered DDR PC3200 mem controller)
(dual core)
2006		 940 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
?v		 Socket 940 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 233 million
0.09µm process
199mm² die


Opteron (Socket 939)
AMD
Processors		 Natural
State		 Sockets L1/L2 Cache
(Associativity)		 Transistors
Opteron 144 MMX 3DNow! SSE SSE2
(Venus - unbuffered)
(128-bit on-Die ECC unbuffered DDR PC3200 mem controller; 8GB max)
August 2, 2005 - {$125}		 939 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
1.4v		 Socket 939 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 114 million
0.09µm process
115mm² die
Opteron 146 MMX 3DNow! SSE SSE2
(Venus - unbuffered)
(128-bit on-Die ECC unbuffered DDR PC3200 mem controller; 8GB max)
August 2, 2005		 939 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.4v		 Socket 939 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 114 million
0.09µm process
115mm² die
Opteron 148 MMX 3DNow! SSE SSE2
(Venus - unbuffered)
(128-bit on-Die ECC unbuffered DDR PC3200 mem controller; 8GB max)
August 2, 2005		 939 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.4v		 Socket 939 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 114 million
0.09µm process
115mm² die
Opteron 150 MMX 3DNow! SSE SSE2
(Venus - unbuffered)
(128-bit on-Die ECC unbuffered DDR PC3200 mem controller; 8GB max)
August 2, 2005		 939 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.4v		 Socket 939 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 114 million
0.09µm process
115mm² die
Opteron 152 MMX 3DNow! SSE SSE2
(Venus - unbuffered)
(128-bit on-Die ECC unbuffered DDR PC3200 mem controller; 8GB max)
August 2, 2005 - {$799}		 939 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
1.4v		 Socket 939 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 114 million
0.09µm process
115mm² die
Opteron 154 MMX 3DNow! SSE SSE2
(Venus - unbuffered)
(128-bit on-Die ECC unbuffered DDR PC3200 mem controller; 8GB max)
2H 2005		 939 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
1.4v		 Socket 939 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		 114 million
0.09µm process
115mm² die

Opteron 165 MMX 3DNow! SSE SSE2 SSE3
(Denmark - unbuffered)
(128-bit on-Die ECC unbuffered DDR PC3200 mem controller)
(dual core)
2H 2005		 939 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
1.35v		 Socket 939 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 233 million
0.09µm process
199mm² die
Opteron 170 MMX 3DNow! SSE SSE2 SSE3
(Denmark - unbuffered)
(128-bit on-Die ECC unbuffered DDR PC3200 mem controller)
(dual core)
2H 2005		 939 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.35v		 Socket 939 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 233 million
0.09µm process
199mm² die
Opteron 175 MMX 3DNow! SSE SSE2 SSE3
(Denmark - unbuffered)
(128-bit on-Die ECC unbuffered DDR PC3200 mem controller)
(dual core)
2H 2005		 939 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.35v		 Socket 939 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 233 million
0.09µm process
199mm² die


Opteron (Socket AM2)
AMD
Processors		 Natural
State		 Sockets L1/L2/L3 Cache
(Associativity)		 Transistors
Opteron 1210 MMX 3DNow! SSE SSE2 SSE3
(Santa Ana)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller)
(dual core)
August 15, 2006 - {$255}		 940 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
1.35v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Opteron 1210 HE MMX 3DNow! SSE SSE2 SSE3
(Santa Ana)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller)
(dual core)
February 7, 2007 - {$168}		 940 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
1.25v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Opteron 1212 MMX 3DNow! SSE SSE2 SSE3
(Santa Ana)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller)
(dual core)
August 15, 2006 - {$377}		 940 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.35v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Opteron 1212 HE MMX 3DNow! SSE SSE2 SSE3
(Santa Ana)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller)
(dual core)
February 7, 2007 - {$209}		 940 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.25v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Opteron 1214 MMX 3DNow! SSE SSE2 SSE3
(Santa Ana)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller)
(dual core)
August 15, 2006 - {$523}		 940 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.35v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Opteron 1214 HE MMX 3DNow! SSE SSE2 SSE3
(Santa Ana)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller)
(dual core)
February 7, 2007 - {$247}		 940 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.25v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Opteron 1216 MMX 3DNow! SSE SSE2 SSE3
(Santa Ana)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller)
(dual core)
August 15, 2006 - {$698}		 940 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.35v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Opteron 1216 HE MMX 3DNow! SSE SSE2 SSE3
(Santa Ana)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller)
(dual core)
February 7, 2007 - {$291}		 940 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.25v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Opteron 1218 MMX 3DNow! SSE SSE2 SSE3
(Santa Ana)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller)
(dual core)
August 15, 2006 - {$873}		 940 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
1.35v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Opteron 1218 HE MMX 3DNow! SSE SSE2 SSE3
(Santa Ana)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller)
(dual core)
February 7, 2007 - {$432}		 940 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
1.25v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Opteron 1220 MMX 3DNow! SSE SSE2 SSE3
(Santa Ana)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller)
(dual core)
February 7, 2007 - {$545}		 940 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
1.35v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Opteron 1220 SE MMX 3DNow! SSE SSE2 SSE3
(Santa Ana)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller)
(dual core)
August 15, 2006 - {$1165}		 940 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
1.4v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Opteron 1222 MMX 3DNow! SSE SSE2 SSE3
(Santa Ana)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller)
(dual core)
2008		 940 pins
3000MHz (200x15)
(64-bit dual-pumped bus)
1.35v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Opteron 1222 SE MMX 3DNow! SSE SSE2 SSE3
(Santa Ana)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller)
(dual core)
2008		 940 pins
3000MHz (200x15)
(64-bit dual-pumped bus)
1.4v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Opteron 1224 SE MMX 3DNow! SSE SSE2 SSE3
(Santa Ana)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller)
(dual core)
2008		 940 pins
3200MHz (200x16)
(64-bit dual-pumped bus)
1.4v		 Socket AM2
Socket AM2+		 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die

Opteron ??? MMX 3DNow! SSE SSE2 SSE3 SSE4
(Budapest)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller)
(quad core, HT 3.0, DICE)
2008?		 940 pins
?MHz (200x?)
(64-bit dual-pumped bus)
?v		 Socket AM2+ 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 ? million
0.065µm process
?mm² die


Opteron (Socket F / Socket G34)
AMD
Processors		 Natural
State		 Sockets L1/L2/L3 Cache
(Associativity)		 Transistors
Opteron 2210 MMX 3DNow! SSE SSE2 SSE3
(Santa Rosa)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(dual core)
August 15, 2006 - {$255}		 1207 balls
1800MHz (200x9)
(64-bit dual-pumped bus)
1.35v		 Socket F 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Opteron 2210 HE MMX 3DNow! SSE SSE2 SSE3
(Santa Rosa)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(dual core)
August 15, 2006 - {$316}		 1207 balls
1800MHz (200x9)
(64-bit dual-pumped bus)
1.25v		 Socket F 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Opteron 2212 MMX 3DNow! SSE SSE2 SSE3
(Santa Rosa)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(dual core)
August 15, 2006 - {$377}		 1207 balls
2000MHz (200x10)
(64-bit dual-pumped bus)
1.35v		 Socket F 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Opteron 2212 HE MMX 3DNow! SSE SSE2 SSE3
(Santa Rosa)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(dual core)
August 15, 2006 - {$450}		 1207 balls
2000MHz (200x10)
(64-bit dual-pumped bus)
1.25v		 Socket F 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Opteron 2214 MMX 3DNow! SSE SSE2 SSE3
(Santa Rosa)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(dual core)
August 15, 2006 - {$523}		 1207 balls
2200MHz (200x11)
(64-bit dual-pumped bus)
1.35v		 Socket F 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Opteron 2214 HE MMX 3DNow! SSE SSE2 SSE3
(Santa Rosa)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(dual core)
August 15, 2006 - {$611}		 1207 balls
2200MHz (200x11)
(64-bit dual-pumped bus)
1.25v		 Socket F 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Opteron 2216 MMX 3DNow! SSE SSE2 SSE3
(Santa Rosa)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(dual core)
August 15, 2006 - {$698}		 1207 balls
2400MHz (200x12)
(64-bit dual-pumped bus)
1.35v		 Socket F 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Opteron 2216 HE MMX 3DNow! SSE SSE2 SSE3
(Santa Rosa)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(dual core)
August 15, 2006 - {$786}		 1207 balls
2400MHz (200x12)
(64-bit dual-pumped bus)
1.25v		 Socket F 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Opteron 2218 MMX 3DNow! SSE SSE2 SSE3
(Santa Rosa)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(dual core)
August 15, 2006 - {$873}		 1207 balls
2600MHz (200x13)
(64-bit dual-pumped bus)
1.35v		 Socket F 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Opteron 2218 HE MMX 3DNow! SSE SSE2 SSE3
(Santa Rosa)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(dual core)
February 7, 2007 - {$611}		 1207 balls
2600MHz (200x13)
(64-bit dual-pumped bus)
1.25v		 Socket F 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Opteron 2220 MMX 3DNow! SSE SSE2 SSE3
(Santa Rosa)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(dual core)
February 7, 2007 - {$698}		 1207 balls
2800MHz (200x14)
(64-bit dual-pumped bus)
1.35v		 Socket F 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Opteron 2220 SE MMX 3DNow! SSE SSE2 SSE3
(Santa Rosa)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(dual core)
August 15, 2006 - {$1165}		 1207 balls
2800MHz (200x14)
(64-bit dual-pumped bus)
1.375v		 Socket F 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Opteron 2222 SE MMX 3DNow! SSE SSE2 SSE3
(Santa Rosa)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(dual core)
2008		 1207 balls
3000MHz (200x15)
(64-bit dual-pumped bus)
1.375v		 Socket F 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Opteron 2224 SE MMX 3DNow! SSE SSE2 SSE3
(Santa Rosa)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(dual core)
2008		 1207 balls
3200MHz (200x16)
(64-bit dual-pumped bus)
1.4v		 Socket F 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die

Opteron 8212 MMX 3DNow! SSE SSE2 SSE3
(Santa Rosa)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(dual core)
August 15, 2006 - {$873}		 1207 balls
2000MHz (200x10)
(64-bit dual-pumped bus)
1.35v		 Socket F 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Opteron 8212 HE MMX 3DNow! SSE SSE2 SSE3
(Santa Rosa)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(dual core)
August 15, 2006 - {$1019}		 1207 balls
2000MHz (200x10)
(64-bit dual-pumped bus)
1.25v		 Socket F 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Opteron 8214 MMX 3DNow! SSE SSE2 SSE3
(Santa Rosa)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(dual core)
August 15, 2006 - {$1165}		 1207 balls
2200MHz (200x11)
(64-bit dual-pumped bus)
1.35v		 Socket F 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Opteron 8214 HE MMX 3DNow! SSE SSE2 SSE3
(Santa Rosa)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(dual core)
August 15, 2006 - {$1340}		 1207 balls
2200MHz (200x11)
(64-bit dual-pumped bus)
1.25v		 Socket F 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Opteron 8216 MMX 3DNow! SSE SSE2 SSE3
(Santa Rosa)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(dual core)
August 15, 2006 - {$1514}		 1207 balls
2400MHz (200x12)
(64-bit dual-pumped bus)
1.35v		 Socket F 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Opteron 8216 HE MMX 3DNow! SSE SSE2 SSE3
(Santa Rosa)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(dual core)
August 15, 2006 - {$1832}		 1207 balls
2400MHz (200x12)
(64-bit dual-pumped bus)
1.25v		 Socket F 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Opteron 8218 MMX 3DNow! SSE SSE2 SSE3
(Santa Rosa)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(dual core)
August 15, 2006 - {$2149}		 1207 balls
2600MHz (200x13)
(64-bit dual-pumped bus)
1.35v		 Socket F 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Opteron 8218 HE MMX 3DNow! SSE SSE2 SSE3
(Santa Rosa)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(dual core)
February 7, 2007 - {$1340}		 1207 balls
2600MHz (200x13)
(64-bit dual-pumped bus)
1.25v		 Socket F 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Opteron 8220 MMX 3DNow! SSE SSE2 SSE3
(Santa Rosa)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(dual core)
February 7, 2007 - {$1514}		 1207 balls
2800MHz (200x14)
(64-bit dual-pumped bus)
1.35v		 Socket F 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Opteron 8220 SE MMX 3DNow! SSE SSE2 SSE3
(Santa Rosa)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(dual core)
August 15, 2006 - {$2649}		 1207 balls
2800MHz (200x14)
(64-bit dual-pumped bus)
1.375v		 Socket F 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Opteron 8222 MMX 3DNow! SSE SSE2 SSE3
(Santa Rosa)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(dual core)
April 9, 2008 - {$1514}		 1207 balls
3000MHz (200x15)
(64-bit dual-pumped bus)
1.35v		 Socket F 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Opteron 8222 SE MMX 3DNow! SSE SSE2 SSE3
(Santa Rosa)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(dual core)
April 9, 2008 - {$1514}		 1207 balls
3000MHz (200x15)
(64-bit dual-pumped bus)
1.375v		 Socket F 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die
Opteron 8224 SE MMX 3DNow! SSE SSE2 SSE3
(Santa Rosa)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(dual core)
April 9, 2008 - {$2149}		 1207 balls
3200MHz (200x16)
(64-bit dual-pumped bus)
1.4v		 Socket F 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		 227 million
0.09µm process
235mm² die

Opteron ??? MMX 3DNow! SSE SSE2 SSE3
( ? )
(128-bit on-Die registered DDR2 PC5400 mem controller)
(dual core)
2008?		 1207 balls
?MHz (200x?)
(64-bit dual-pumped bus)
?v		 Socket F 2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)
?MB on-Die shared L3 (32-way)		 ? million
0.065µm process
?mm² die

Opteron ??? MMX 3DNow! SSE SSE2 SSE3
(Deerhound)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(quad core)
2008?		 1207 balls
?MHz (200x?)
(64-bit dual-pumped bus)
?v		 Socket F 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)		 ? million
0.065µm process
?mm² die

Opteron 1352 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Barcelona)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(quad core)
June 3, 2008 - {$209}		 1207 balls
2100MHz (200x10.5)
(64-bit dual-pumped bus)
?v		 Socket F 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die
Opteron 1354 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Barcelona)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(quad core)
June 3, 2008 - {$255}		 1207 balls
2200MHz (200x11)
(64-bit dual-pumped bus)
?v		 Socket F 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die
Opteron 1356 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Barcelona)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(quad core)
June 3, 2008 - {$377}		 1207 balls
2300MHz (200x11.5)
(64-bit dual-pumped bus)
?v		 Socket F 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die

Opteron 2258 HE MMX 3DNow! SSE SSE2 SSE3 SSE4
(Barcelona)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(quad core)
2008?		 1207 balls
?MHz (200x?)
(64-bit dual-pumped bus)
?v		 Socket F 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die
Opteron 2344 HE MMX 3DNow! SSE SSE2 SSE3 SSE4
(Barcelona)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(quad core)
September 10, 2007		 1207 balls
1700MHz (200x8.5)
(64-bit dual-pumped bus)
1.15v		 Socket F 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die
Opteron 2346 HE MMX 3DNow! SSE SSE2 SSE3 SSE4
(Barcelona)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(quad core)
September 10, 2007		 1207 balls
1800MHz (200x9)
(64-bit dual-pumped bus)
1.15v		 Socket F 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die
Opteron 2347 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Barcelona)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(quad core)
September 10, 2007		 1207 balls
1900MHz (200x9.5)
(64-bit dual-pumped bus)
1.2v		 Socket F 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die
Opteron 2347 HE MMX 3DNow! SSE SSE2 SSE3 SSE4
(Barcelona)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(quad core)
September 10, 2007		 1207 balls
1900MHz (200x9.5)
(64-bit dual-pumped bus)
1.15v		 Socket F 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die
Opteron 2350 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Barcelona)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(quad core)
September 10, 2007		 1207 balls
2000MHz (200x10)
(64-bit dual-pumped bus)
1.2v		 Socket F 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die
Opteron 2352 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Barcelona)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(quad core)
April 9, 2008 - {$316}		 1207 balls
2100MHz (200x10.5)
(64-bit dual-pumped bus)
1.2v		 Socket F 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die
Opteron 2354 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Barcelona)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(quad core)
April 9, 2008 - {$455}		 1207 balls
2200MHz (200x11)
(64-bit dual-pumped bus)
1.2v		 Socket F 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die
Opteron 2356 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Barcelona)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(quad core)
April 9, 2008 - {$690}		 1207 balls
2300MHz (200x11.5)
(64-bit dual-pumped bus)
1.2v		 Socket F 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die
Opteron 2358 SE MMX 3DNow! SSE SSE2 SSE3 SSE4
(Barcelona)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(quad core)
April 9, 2008 - {$873}		 1207 balls
2400MHz (200x12)
(64-bit dual-pumped bus)
?v		 Socket F 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die
Opteron 2360 SE MMX 3DNow! SSE SSE2 SSE3 SSE4
(Barcelona)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(quad core)
April 9, 2008 - {$1165}		 1207 balls
2500MHz (200x12.5)
(64-bit dual-pumped bus)
?v		 Socket F 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die

Opteron 8346 HE MMX 3DNow! SSE SSE2 SSE3 SSE4
(Barcelona)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(quad core)
September 10, 2007		 1207 balls
1800MHz (200x9)
(64-bit dual-pumped bus)
1.15v		 Socket F 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die
Opteron 8347 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Barcelona)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(quad core)
September 10, 2007		 1207 balls
1900MHz (200x9.5)
(64-bit dual-pumped bus)
1.2v		 Socket F 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die
Opteron 8347 HE MMX 3DNow! SSE SSE2 SSE3 SSE4
(Barcelona)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(quad core)
September 10, 2007		 1207 balls
1900MHz (200x9.5)
(64-bit dual-pumped bus)
1.15v		 Socket F 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die
Opteron 8350 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Barcelona)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(quad core)
September 10, 2007		 1207 balls
2000MHz (200x10)
(64-bit dual-pumped bus)
1.2v		 Socket F 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die
Opteron 8354 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Barcelona)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(quad core)
April 9, 2008 - {$1165}		 1207 balls
2200MHz (200x11)
(64-bit dual-pumped bus)
1.2v		 Socket F 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die
Opteron 8356 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Barcelona)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(quad core)
April 9, 2008 - {$1514}		 1207 balls
2300MHz (200x11.5)
(64-bit dual-pumped bus)
1.2v		 Socket F 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die
Opteron 8358 SE MMX 3DNow! SSE SSE2 SSE3 SSE4
(Barcelona)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(quad core)
April 9, 2008 - {$1865}		 1207 balls
2400MHz (200x12)
(64-bit dual-pumped bus)
?v		 Socket F 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die
Opteron 8360 SE MMX 3DNow! SSE SSE2 SSE3 SSE4
(Barcelona)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(quad core)
April 9, 2008 - {$2149}		 1207 balls
2500MHz (200x12.5)
(64-bit dual-pumped bus)
?v		 Socket F 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die
Opteron ??? MMX 3DNow! SSE SSE2 SSE3 SSE4
(Barcelona)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(quad core)
2008?		 1207 balls
?MHz (200x?)
(64-bit dual-pumped bus)
?v		 Socket F 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 463 million
0.065µm process
288mm² die

Opteron ??? MMX 3DNow! SSE SSE2 SSE3 SSE4
(Istanbul)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(6 cores, HT 3.0, DICE)
2H 2009?		 1207 balls
?MHz (200x?)
(64-bit dual-pumped bus)
?v		 Socket F+ 6x 64KB data (2-way)
6x 64KB instruction (2-way)
6x ?KB on-Die unified L2 (16-way exclusive)		 ? million
0.045µm process
?mm² die

Opteron ??? MMX 3DNow! SSE SSE2 SSE3 SSE4
(Shanghai)
(128-bit on-Die registered DDR2 PC5400 mem controller)
(quad core, HT 3.0, DICE)
2H 2008?		 1207 pins
?MHz (200x?)
(64-bit dual-pumped bus)
?v		 Socket F+ 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		 ? million
0.045µm process
243mm² die

Opteron ??? MMX 3DNow! SSE SSE2 SSE3 SSE4
(Greyhound)
(128-bit on-Die registered DDR2 PC5400, or FBD mem controller)
(quad core, HT 3.0, DICE)
2008?		 1207 balls
?MHz (200x?)
(64-bit dual-pumped bus)
?v		 Socket F+ 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 ? million
?µm process
?mm² die

Opteron ??? MMX 3DNow! SSE SSE2 SSE3 SSE4
(Zamora)
(128-bit on-Die FBD mem controller)
(quad core, HT 3.0, DICE)
2008?		 1207 balls
?MHz (200x?)
(64-bit dual-pumped bus)
?v		 Socket F+ 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		 ? million
?µm process
?mm² die

Opteron ??? MMX 3DNow! SSE SSE2 SSE3 SSE4
(Cadiz)
(128-bit on-Die registered DDR2/3 PC5400 mem controller)
(quad core, HT 3.0, DICE)
2008?		 1207 balls
?MHz (200x?)
(64-bit dual-pumped bus)
?v		 Socket F+ 4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)		 ? million
?µm process
?mm² die

Opteron ??? MMX 3DNow! SSE SSE2 SSE3 SSE4
(Sandtiger)
(128-bit on-Die registered DDR3 PC5400 mem controller)
(8 cores, HT 3.0, DICE)
2009?		 1207 balls
?MHz (200x?)
(64-bit dual-pumped bus)
?v		 Socket F+ 8x 64KB data (2-way)
8x 64KB instruction (2-way)
8x ?KB on-Die unified L2 (16-way exclusive)		 ? million
0.045µm process
?mm² die

Opteron ??? MMX 3DNow! SSE SSE2 SSE3 SSE4
(Sao Paolo)
(128-bit on-Die registered DDR3 PC5400 mem controller)
(6 cores, HT 3.0, DICE)
1H 2010?		 1944 balls
?MHz (200x?)
(64-bit dual-pumped bus)
?v		 Socket G34 6x 64KB data (2-way)
6x 64KB instruction (2-way)
6x ?KB on-Die unified L2 (16-way exclusive)		 ? million
?µm process
?mm² die

Opteron ??? MMX 3DNow! SSE SSE2 SSE3 SSE4
(Montreal)
(128-bit on-Die registered DDR3 PC5400 mem controller)
(8 cores, HT 3.0, DICE)
2009?		 1944 balls
?MHz (200x?)
(64-bit dual-pumped bus)
?v		 Socket G34 8x 64KB data (2-way)
8x 64KB instruction (2-way)
8x 1MB on-Die unified L2 (16-way exclusive)
12MB on-Die shared L3 (?-way)		 ? million
?µm process
?mm² die

Opteron ??? MMX 3DNow! SSE SSE2 SSE3 SSE4
(Magny Cours)
(128-bit on-Die registered DDR3 PC5400 mem controller)
(12 cores, HT 3.0, DICE)
2010?		 1944 balls
?MHz (200x?)
(64-bit dual-pumped bus)
?v		 Socket G34 12x 64KB data (2-way)
12x 64KB instruction (2-way)
12x ?KB on-Die unified L2 (16-way exclusive)		 ? million
?µm process
?mm² die


Intel Desktop


Core 2 (Socket 775)
Intel
Processors		 Natural
State		 Sockets L1/L2 Cache
(Associativity)		 Transistors
Celeron D 420 MMX SSE SSE2 SSE3
(Conroe-L)
(EM64T, NX bit)
June 3, 2007 - {$39}		 775 balls
1600MHz (200x8)
(64-bit quad-pumped bus)
?v		 Socket 775 32KB data (8-way)
32KB instruction (8-way)
512KB on-Die unified L2 (2-way)		 ? million
0.065µm process
?mm² die
Celeron D 430 MMX SSE SSE2 SSE3
(Conroe-L)
(EM64T, NX bit)
June 3, 2007 - {$49}		 775 balls
1800MHz (200x9)
(64-bit quad-pumped bus)
?v		 Socket 775 32KB data (8-way)
32KB instruction (8-way)
512KB on-Die unified L2 (2-way)		 ? million
0.065µm process
?mm² die
Celeron D 440 MMX SSE SSE2 SSE3
(Conroe-L)
(EM64T, NX bit)
June 3, 2007 - {$59}		 775 balls
2000MHz (200x10)
(64-bit quad-pumped bus)
?v		 Socket 775 32KB data (8-way)
32KB instruction (8-way)
512KB on-Die unified L2 (2-way)		 ? million
0.065µm process
?mm² die

Celeron E1200 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit)
January 7, 2008		 775 balls
1600MHz (200x8)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
512KB on-Die shared L2 (2-way)		 291 million
0.065µm process
143mm² die
Celeron E1600 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit)
2008?		 775 balls
2000MHz (200x10)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
512KB on-Die shared L2 (2-way)		 291 million
0.065µm process
143mm² die
Intel
Processors		 Natural
State		 Sockets L1/L2 Cache
(Associativity)		 Transistors
Pentium E2140 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit)
June 3, 2007 - {$74}		 775 balls
1600MHz (200x8)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
1MB on-Die shared L2 (4-way)		 291 million
0.065µm process
143mm² die
Pentium E2160 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit)
June 3, 2007 - {$84}		 775 balls
1800MHz (200x9)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
1MB on-Die shared L2 (4-way)		 291 million
0.065µm process
143mm² die
Pentium E2180 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit)
August 27, 2007 - {$84}		 775 balls
2000MHz (200x10)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
1MB on-Die shared L2 (4-way)		 291 million
0.065µm process
143mm² die
Pentium E2200 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit)
December, 2007 - {$84}		 775 balls
2200MHz (200x11)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
1MB on-Die shared L2 (4-way)		 291 million
0.065µm process
143mm² die
Pentium E2220 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit)
March 6, 2008		 775 balls
2400MHz (200x12)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
1MB on-Die shared L2 (4-way)		 291 million
0.065µm process
143mm² die
Intel
Processors		 Natural
State		 Sockets L1/L2 Cache
(Associativity)		 Transistors
Core 2 Duo E4300 MMX SSE SSE2 SSE3
(Allendale)
(dual core, EM64T, NX bit)
January 7, 2007 - ($183}		 775 balls
1800MHz (200x9)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
2MB on-Die shared L2 (8-way)		 167 million
0.065µm process
111mm² die
Core 2 Duo E4400 MMX SSE SSE2 SSE3
(Allendale)
(dual core, EM64T, NX bit)
April 22, 2007 - {$133}		 775 balls
2000MHz (200x10)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
2MB on-Die shared L2 (8-way)		 167 million
0.065µm process
111mm² die
Core 2 Duo E4500 MMX SSE SSE2 SSE3
(Allendale)
(dual core, EM64T, NX bit)
July 16, 2007		 775 balls
2200MHz (200x11)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
2MB on-Die shared L2 (8-way)		 167 million
0.065µm process
111mm² die
Core 2 Duo E4600 MMX SSE SSE2 SSE3
(Allendale)
(dual core, EM64T, NX bit)
October 22, 2007		 775 balls
2400MHz (200x12)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
2MB on-Die shared L2 (8-way)		 167 million
0.065µm process
111mm² die
Core 2 Duo E4700 MMX SSE SSE2 SSE3
(Allendale)
(dual core, EM64T, NX bit)
March 6, 2008		 775 balls
2600MHz (200x13)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
2MB on-Die shared L2 (8-way)		 167 million
0.065µm process
111mm² die

Core 2 Duo E5200 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit)
2008?		 775 balls
2500MHz (200x12.5)
(64-bit quad-pumped bus)
?v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
2MB on-Die shared L2 (8-way)		 228 million
0.045µm process
?mm² die

Core 2 Duo E6300 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit, VT)
July 27, 2006 - ($183}		 775 balls
1866MHz (266x7)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
2MB on-Die shared L2 (8-way)		 291 million
0.065µm process
143mm² die
Core 2 Duo E6320 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit, VT)
April 22, 2007 - {$163}		 775 balls
1866MHz (266x7)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)		 291 million
0.065µm process
143mm² die
Core 2 Duo E6400 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit, VT)
July 27, 2006 - ($224}		 775 balls
2133MHz (266x8)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
2MB on-Die shared L2 (8-way)		 291 million
0.065µm process
143mm² die
Core 2 Duo E6420 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit, VT)
April 22, 2007 - {$183}		 775 balls
2133MHz (266x8)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)		 291 million
0.065µm process
143mm² die
Core 2 Duo E6540 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit, VT)
July 16, 2007		 775 balls
2333MHz (333x7)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)		 291 million
0.065µm process
143mm² die
Core 2 Duo E6550 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit, VT, TXT)
July 16, 2007 - {$163}		 775 balls
2333MHz (333x7)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)		 291 million
0.065µm process
143mm² die
Core 2 Duo E6600 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit, VT)
July 27, 2006 - ($316}		 775 balls
2400MHz (266x9)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)		 291 million
0.065µm process
143mm² die
Core 2 Duo E6700 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit, VT)
July 27, 2006 - ($530}		 775 balls
2666MHz (266x10)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)		 291 million
0.065µm process
143mm² die
Core 2 Duo E6750 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit, VT, TXT)
July 16, 2007 - {$183}		 775 balls
2666MHz (333x8)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)		 291 million
0.065µm process
143mm² die
Core 2 Duo E6850 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit, VT, TXT)
July 16, 2007 - {$266}		 775 balls
3000MHz (333x9)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)		 291 million
0.065µm process
143mm² die

Core 2 Duo E7200 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit)
April, 2008 - {$133}		 775 balls
2533MHz (266x9.5)
(64-bit quad-pumped bus)
?v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
3MB on-Die shared L2 (12-way)		 228 million
0.045µm process
?mm² die
Core 2 Duo E7300 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit)
3Q 2008 - {$133}		 775 balls
?MHz (266x?)
(64-bit quad-pumped bus)
?v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)		 228 million
0.045µm process
?mm² die

Core 2 Duo E8190 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit)
January 7, 2008 - {$163}		 775 balls
2666MHz (333x8)
(64-bit quad-pumped bus)
?v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
6MB on-Die shared L2 (24-way)		 410 million
0.045µm process
107mm² die
Core 2 Duo E8200 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit, VT, TXT)
January 7, 2008 - {$163}		 775 balls
2666MHz (333x8)
(64-bit quad-pumped bus)
?v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
6MB on-Die shared L2 (24-way)		 410 million
0.045µm process
107mm² die
Core 2 Duo E8300 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit, VT, TXT)
April, 2008 - {$163}		 775 balls
2833MHz (333x8.5)
(64-bit quad-pumped bus)
?v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
6MB on-Die shared L2 (24-way)		 410 million
0.045µm process
107mm² die
Core 2 Duo E8400 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit, VT, TXT)
January 7, 2008 - {$183}		 775 balls
3000MHz (333x9)
(64-bit quad-pumped bus)
?v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
6MB on-Die shared L2 (24-way)		 410 million
0.045µm process
107mm² die
Core 2 Duo E8500 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit, VT, TXT)
January 7, 2008 - {$266}		 775 balls
3166MHz (333x9.5)
(64-bit quad-pumped bus)
?v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
6MB on-Die shared L2 (24-way)		 410 million
0.045µm process
107mm² die
Core 2 Duo E8600 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit, VT, TXT)
3Q 2008 - {$266}		 775 balls
3333MHz (333x10)
(64-bit quad-pumped bus)
?v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
6MB on-Die shared L2 (24-way)		 410 million
0.045µm process
107mm² die

Core 2 Duo ??? MMX SSE SSE2 SSE3 SSE4
(Ridgefield)
(dual core, EM64T, NX bit, VT)
2008?		 775 balls
?MHz (400x?)
(64-bit quad-pumped bus)
?v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
6MB on-Die shared L2 (24-way)		 ? million
0.045µm process
?mm² die
Intel
Processors		 Natural
State		 Sockets L1/L2 Cache
(Associativity)		 Transistors
Core 2 Extreme X6800 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit, VT)
July 27, 2006 - {$999}		 775 balls
2933MHz (266x11)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)		 291 million
0.065µm process
143mm² die

Core 2 Quad-Q6400 MMX SSE SSE2 SSE3
(Kentsfield)
(quad core (dual die), EM64T, NX bit, VT)
2008?		 775 balls
2133MHz (266x8)
(64-bit quad-pumped bus)
?v		 Socket 775 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 4MB on-Die shared L2 (16-way)		 582 million
0.065µm process
284mm² die
Core 2 Quad Q6600 MMX SSE SSE2 SSE3
(Kentsfield)
(quad core (dual die), EM64T, NX bit, VT)
January 8, 2007 - {$851}		 775 balls
2400MHz (266x9)
(64-bit quad-pumped bus)
?v		 Socket 775 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 4MB on-Die shared L2 (16-way)		 582 million
0.065µm process
284mm² die
Core 2 Quad Q6700 MMX SSE SSE2 SSE3
(Kentsfield)
(quad core (dual die), EM64T, NX bit, VT)
July 16, 2007 - {$530}		 775 balls
2666MHz (266x10)
(64-bit quad-pumped bus)
?v		 Socket 775 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 4MB on-Die shared L2 (16-way)		 582 million
0.065µm process
284mm² die
Core 2 Extreme QX6700 MMX SSE SSE2 SSE3
(Kentsfield)
(quad core (dual die), EM64T, NX bit, VT)
November 14, 2006 - {$999}		 775 balls
2666MHz (266x10)
(64-bit quad-pumped bus)
?v		 Socket 775 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 4MB on-Die shared L2 (16-way)		 582 million
0.065µm process
284mm² die
Core 2 Extreme QX6800 MMX SSE SSE2 SSE3
(Kentsfield)
(quad core (dual die), EM64T, NX bit, VT)
April 9, 2006 - {$1199}		 775 balls
2933MHz (266x11)
(64-bit quad-pumped bus)
?v		 Socket 775 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 4MB on-Die shared L2 (16-way)		 582 million
0.065µm process
284mm² die
Core 2 Extreme QX6850 MMX SSE SSE2 SSE3
(Kentsfield)
(quad core (dual die), EM64T, NX bit, VT, TXT)
July 16, 2007 - {$999}		 775 balls
3000MHz (333x9)
(64-bit quad-pumped bus)
?v		 Socket 775 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 4MB on-Die shared L2 (16-way)		 582 million
0.065µm process
284mm² die
Core 2 Extreme QX6??? MMX SSE SSE2 SSE3
(Kentsfield)
(quad core (dual die), EM64T, NX bit, VT)
2008?		 775 balls
?MHz (?x?)
(64-bit quad-pumped bus)
?v		 Socket 775 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 4MB on-Die shared L2 (16-way)		 582 million
0.065µm process
284mm² die

Core 2 Quad Q8??? MMX SSE SSE2 SSE3
( ? )
(quad core (dual die), EM64T, NX bit, VT, TXT)
2008?		 775 balls
?MHz (333x?)
(64-bit quad-pumped bus)
?v		 Socket 775 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 2MB on-Die shared L2 (8-way)		 ? million
0.045µm process
?mm² die

Core 2 Quad Q9300 MMX SSE SSE2 SSE3 SSE4
(Yorkfield)
(quad core (dual die), EM64T, NX bit, VT, TXT)
January 7, 2008 - {$266}		 775 balls
2500MHz (333x7.5)
(64-bit quad-pumped bus)
?v		 Socket 775 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 3MB on-Die shared L2 (12-way)		 820 million
0.045µm process
214mm² die
Core 2 Quad Q9400 MMX SSE SSE2 SSE3 SSE4
(Yorkfield)
(quad core (dual die), EM64T, NX bit, VT, TXT)
3Q 2008 - {$266}		 775 balls
2666MHz (333x8)
(64-bit quad-pumped bus)
?v		 Socket 775 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 4MB on-Die shared L2 (16-way)		 820 million
0.045µm process
214mm² die
Core 2 Quad Q9450 MMX SSE SSE2 SSE3 SSE4
(Yorkfield)
(quad core (dual die), EM64T, NX bit, VT, TXT)
January 7, 2008 - {$316}		 775 balls
2666MHz (333x8)
(64-bit quad-pumped bus)
?v		 Socket 775 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 6MB on-Die shared L2 (24-way)		 820 million
0.045µm process
214mm² die
Core 2 Quad Q9550 MMX SSE SSE2 SSE3 SSE4
(Yorkfield)
(quad core (dual die), EM64T, NX bit, VT, TXT)
January 7, 2008 - {$530}		 775 balls
2833MHz (333x8.5)
(64-bit quad-pumped bus)
?v		 Socket 775 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 6MB on-Die shared L2 (24-way)		 820 million
0.045µm process
214mm² die
Core 2 Extreme QX9650 MMX SSE SSE2 SSE3 SSE4
(Yorkfield)
(quad core (dual die), EM64T, NX bit, VT)
November 11, 2007 - {$999}		 775 balls
3000MHz (333x9)
(64-bit quad-pumped bus)
?v		 Socket 775 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 6MB on-Die shared L2 (24-way)		 820 million
0.045µm process
214mm² die
Core 2 Extreme QX9770 MMX SSE SSE2 SSE3 SSE4
(Yorkfield)
(quad core (dual die), EM64T, NX bit, VT)
March 24, 2008 - {$1399}		 775 balls
3200MHz (400x8)
(64-bit quad-pumped bus)
?v		 Socket 775 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 6MB on-Die shared L2 (24-way)		 820 million
0.045µm process
214mm² die
Core 2 Extreme ??? MMX SSE SSE2 SSE3 SSE4
(Yorkfield)
(quad core (dual die), EM64T, NX bit, VT)
2008?		 775 balls
?MHz (400x?)
(64-bit quad-pumped bus)
?v		 Socket 775 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 6MB on-Die shared L2 (24-way)		 820 million
0.045µm process
214mm² die

Core 2 Extreme QX9775 MMX SSE SSE2 SSE3 SSE4
(Harpertown)
(quad core (dual die), EM64T, NX bit, VT)
February 19, 2008 - {$1499}		 771 balls
3200MHz (400x8)
(64-bit quad-pumped bus)
?v		 Socket 771 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 6MB on-Die shared L2 (24-way)		 820 million
0.045µm process
214mm² die

Core 2 Extreme QX???? MMX SSE SSE2 SSE3 SSE4
( ? )
(quad core, EM64T, NX bit, VT)
2008?		 775 balls
?MHz (?x?)
(64-bit quad-pumped bus)
?v		 Socket 775 4x 32KB data (8-way)
4x 32KB instruction (8-way)
4x ?MB on-Die unified L2 (?-way)		 ? million
0.045µm process
?mm² die


Core 2 (Nehalem)
Intel
Processors		 Natural
State		 Sockets L1/L2/L3 Cache
(Associativity)		 Transistors
Core 2 ??? MMX SSE SSE2 SSE3 SSE4.2
(Lynnfield)
(dual core, EM64T, NX bit, VT)
2008?		 715 balls
?MHz (400x?)
(64-bit quad-pumped bus)
?v		 Socket 715 2x 32KB data (8-way)
2x 32KB instruction (4-way)
2x 256KB on-Die unified L2 (8-way)
?MB on-Die shared L3 (16-way)		 ? million
0.045µm process
?mm² die

Core 2 ??? MMX SSE SSE2 SSE3 SSE4.2
(Auburndale)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, EM64T, NX bit, VT)
2008?		 1160 balls
?MHz (400x?)
(64-bit quad-pumped bus)
?v		 Socket 1160 2x 32KB data (8-way)
2x 32KB instruction (4-way)
2x 256KB on-Die unified L2 (8-way)
4MB on-Die shared L3 (16-way)		 ? million
0.045µm process
?mm² die

Core 2 ??? MMX SSE SSE2 SSE3 SSE4.2
(Bloomfield)
192-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, SMT Hyperthreading, EM64T, NX bit, VT)
2H 2008?		 1366 balls
?MHz (400x?)
(64-bit quad-pumped bus)
?v		 Socket 1366 4x 32KB data (8-way)
4x 32KB instruction (4-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)		 731 million
0.045µm process
246mm² die


Intel Server


Xeon (Socket 775)
Intel
Processors		 Natural
State		 Sockets L1/L2 Cache
(Associativity)		 Transistors
Xeon 3040 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit, VT)
September 26, 2006		 775 balls
1866MHz (266x7)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
2MB on-Die shared L2 (8-way)		 291 million
0.065µm process
143mm² die
Xeon 3050 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit, VT)
September 26, 2006		 775 balls
2133MHz (266x8)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
2MB on-Die shared L2 (8-way)		 291 million
0.065µm process
143mm² die
Xeon 3060 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit, VT)
September 26, 2006		 775 balls
2400MHz (266x9)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)		 291 million
0.065µm process
143mm² die
Xeon 3065 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit, VT)
November 11, 2007		 775 balls
2666MHz (333x7)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)		 291 million
0.065µm process
143mm² die
Xeon 3070 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit, VT)
September 26, 2006		 775 balls
2666MHz (266x10)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)		 291 million
0.065µm process
143mm² die
Xeon 3075 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit, VT)
November 11, 2007		 775 balls
2666MHz (333x8)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)		 291 million
0.065µm process
143mm² die
Xeon 3085 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit, VT)
November 11, 2007		 775 balls
3000MHz (333x9)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)		 291 million
0.065µm process
143mm² die

Xeon E3110 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit, VT)
January, 2008		 775 balls
3000MHz (333x9)
(64-bit quad-pumped bus)
?v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
6MB on-Die shared L2 (24-way)		 410 million
0.045µm process
107mm² die

Xeon X3210 MMX SSE SSE2 SSE3
(Kentsfield)
(quad core (dual die), EM64T, NX bit, VT)
January 8, 2007 - {$690}		 775 balls
2133MHz (266x8)
(64-bit quad-pumped bus)
?v		 Socket 775 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 4MB on-Die shared L2 (16-way)		 582 million
0.065µm process
284mm² die
Xeon X3220 MMX SSE SSE2 SSE3
(Kentsfield)
(quad core (dual die), EM64T, NX bit, VT)
January 8, 2007 - {$851}		 775 balls
2400MHz (266x9)
(64-bit quad-pumped bus)
?v		 Socket 775 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 4MB on-Die shared L2 (16-way)		 582 million
0.065µm process
284mm² die
Xeon X3230 MMX SSE SSE2 SSE3
(Kentsfield)
(quad core (dual die), EM64T, NX bit, VT)
3Q 2007		 775 balls
2666MHz (266x10)
(64-bit quad-pumped bus)
?v		 Socket 775 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 4MB on-Die shared L2 (16-way)		 582 million
0.065µm process
284mm² die

Xeon X3320 MMX SSE SSE2 SSE3 SSE4
(Yorkfield)
(quad core (dual die), EM64T, NX bit, VT)
March 24, 2008 - {$266}		 775 balls
2500MHz (333x7.5)
(64-bit quad-pumped bus)
?v		 Socket 775 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 3MB on-Die shared L2 (12-way)		 820 million
0.045µm process
214mm² die
Xeon X3350 MMX SSE SSE2 SSE3 SSE4
(Yorkfield)
(quad core (dual die), EM64T, NX bit, VT)
March 24, 2008 - {$316}		 775 balls
2666MHz (333x8)
(64-bit quad-pumped bus)
?v		 Socket 775 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 6MB on-Die shared L2 (24-way)		 820 million
0.045µm process
214mm² die
Xeon X3360 MMX SSE SSE2 SSE3 SSE4
(Yorkfield)
(quad core (dual die), EM64T, NX bit, VT)
March 24, 2008 - {$530}		 775 balls
2833MHz (333x8.5)
(64-bit quad-pumped bus)
?v		 Socket 775 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 6MB on-Die shared L2 (24-way)		 820 million
0.045µm process
214mm² die


Xeon (Socket 771)
Intel
Processors		 Natural
State		 Sockets L1/L2 Cache
(Associativity)		 Transistors
Xeon 5020 MMX SSE SSE2 SSE3
(Dempsey)
(dual die, Jackson Hyperthreading, EM64T, NX bit)		 771 balls
2500MHz (166x15)
(64-bit quad-pumped bus)
?v		 Socket 771 2x 16KB data (8-way)
2x 12k µops trace instruction (8-way)
2x 2MB on-Die unified L2 (8-way)		 230 million
0.065µm process
206mm² die
Xeon 5030 MMX SSE SSE2 SSE3
(Dempsey)
(dual die, Jackson Hyperthreading, EM64T, NX bit, VT)
May 23, 2006		 771 balls
2666MHz (166x16)
(64-bit quad-pumped bus)
?v		 Socket 771 2x 16KB data (8-way)
2x 12k µops trace instruction (8-way)
2x 2MB on-Die unified L2 (8-way)		 230 million
0.065µm process
206mm² die
Xeon 5040 MMX SSE SSE2 SSE3
(Dempsey)
(dual die, Jackson Hyperthreading, EM64T, NX bit)		 771 balls
2833MHz (166x17)
(64-bit quad-pumped bus)
?v		 Socket 771 2x 16KB data (8-way)
2x 12k µops trace instruction (8-way)
2x 2MB on-Die unified L2 (8-way)		 230 million
0.065µm process
206mm² die
Xeon 5050 MMX SSE SSE2 SSE3
(Dempsey)
(dual die, Jackson Hyperthreading, EM64T, NX bit, VT)
May 23, 2006		 771 balls
3000MHz (166x18)
(64-bit quad-pumped bus)
?v		 Socket 771 2x 16KB data (8-way)
2x 12k µops trace instruction (8-way)
2x 2MB on-Die unified L2 (8-way)		 230 million
0.065µm process
206mm² die
Xeon 5060 MMX SSE SSE2 SSE3
(Dempsey)
(dual die, Jackson Hyperthreading, EM64T, NX bit, VT)
May 23, 2006		 771 balls
3200MHz (266x12)
(64-bit quad-pumped bus)
?v		 Socket 771 2x 16KB data (8-way)
2x 12k µops trace instruction (8-way)
2x 2MB on-Die unified L2 (8-way)		 230 million
0.065µm process
206mm² die
Xeon 5063 MMX SSE SSE2 SSE3
(Dempsey)
(dual die, Jackson Hyperthreading, EM64T, NX bit, VT)
May 23, 2006		 771 balls
3200MHz (266x12)
(64-bit quad-pumped bus)
?v		 Socket 771 2x 16KB data (8-way)
2x 12k µops trace instruction (8-way)
2x 2MB on-Die unified L2 (8-way)		 230 million
0.065µm process
206mm² die
Xeon 5070 MMX SSE SSE2 SSE3
(Dempsey)
(dual die, Jackson Hyperthreading, EM64T, NX bit)		 771 balls
3466MHz (266x13)
(64-bit quad-pumped bus)
?v		 Socket 771 2x 16KB data (8-way)
2x 12k µops trace instruction (8-way)
2x 2MB on-Die unified L2 (8-way)		 230 million
0.065µm process
206mm² die
Xeon 5080 MMX SSE SSE2 SSE3
(Dempsey)
(dual die, Jackson Hyperthreading, EM64T, NX bit, VT)
May 23, 2006		 771 balls
3733MHz (266x14)
(64-bit quad-pumped bus)
?v		 Socket 771 2x 16KB data (8-way)
2x 12k µops trace instruction (8-way)
2x 2MB on-Die unified L2 (8-way)		 230 million
0.065µm process
206mm² die

Xeon LV 5128 MMX SSE SSE2 SSE3
(Woodcrest)
(dual core, EM64T, NX bit, VT)
December 1, 2006		 771 balls
1866MHz (266x7)
(64-bit quad-pumped bus)
?v		 Socket 771 2x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)		 291 million
0.065µm process
143mm² die
Xeon LV 5138 MMX SSE SSE2 SSE3
(Woodcrest)
(dual core, EM64T, NX bit, VT)
December 1, 2006		 771 balls
2133MHz (266x8)
(64-bit quad-pumped bus)
?v		 Socket 771 2x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)		 291 million
0.065µm process
143mm² die
Xeon LV 5148 MMX SSE SSE2 SSE3
(Woodcrest)
(dual core, EM64T, NX bit, VT)
June 26, 2006		 771 balls
2333MHz (333x7)
(64-bit quad-pumped bus)
?v		 Socket 771 2x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)		 291 million
0.065µm process
143mm² die
Xeon 5110 MMX SSE SSE2 SSE3
(Woodcrest)
(dual core, EM64T, NX bit, VT)
June 26, 2006		 771 balls
1600MHz (266x6)
(64-bit quad-pumped bus)
?v		 Socket 771 2x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)		 291 million
0.065µm process
143mm² die
Xeon 5120 MMX SSE SSE2 SSE3
(Woodcrest)
(dual core, EM64T, NX bit, VT)
June 26, 2006		 771 balls
1866MHz (266x7)
(64-bit quad-pumped bus)
?v		 Socket 771 2x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)		 291 million
0.065µm process
143mm² die
Xeon 5130 MMX SSE SSE2 SSE3
(Woodcrest)
(dual core, EM64T, NX bit, VT)
June 26, 2006		 771 balls
2000MHz (333x6)
(64-bit quad-pumped bus)
?v		 Socket 771 2x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)		 291 million
0.065µm process
143mm² die
Xeon 5140 MMX SSE SSE2 SSE3
(Woodcrest)
(dual core, EM64T, NX bit, VT)
June 26, 2006		 771 balls
2333MHz (333x7)
(64-bit quad-pumped bus)
?v		 Socket 771 2x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)		 291 million
0.065µm process
143mm² die
Xeon 5150 MMX SSE SSE2 SSE3
(Woodcrest)
(dual core, EM64T, NX bit, VT)
June 26, 2006		 771 balls
2666MHz (333x8)
(64-bit quad-pumped bus)
?v		 Socket 771 2x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)		 291 million
0.065µm process
143mm² die
Xeon 5160 MMX SSE SSE2 SSE3
(Woodcrest)
(dual core, EM64T, NX bit, VT)
June 26, 2006		 771 balls
3000MHz (333x9)
(64-bit quad-pumped bus)
?v		 Socket 771 2x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)		 291 million
0.065µm process
143mm² die

Xeon L5238 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit, VT)
February 27, 2008		 771 balls
2666MHz (333x8)
(64-bit quad-pumped bus)
?v		 Socket 771 2x 32KB data (8-way)
2x 32KB instruction (8-way)
6MB on-Die shared L2 (24-way)		 410 million
0.045µm process
107mm² die
Xeon L5240 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit, VT)
2008		 771 balls
3000MHz (333x9)
(64-bit quad-pumped bus)
?v		 Socket 771 2x 32KB data (8-way)
2x 32KB instruction (8-way)
6MB on-Die shared L2 (24-way)		 410 million
0.045µm process
107mm² die
Xeon E5205 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit, VT)
November 11, 2007 - {$177}		 771 balls
1866MHz (266x7)
(64-bit quad-pumped bus)
?v		 Socket 771 2x 32KB data (8-way)
2x 32KB instruction (8-way)
6MB on-Die shared L2 (24-way)		 410 million
0.045µm process
107mm² die
Xeon E5220 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit, VT)
February 27, 2008		 771 balls
2333MHz (333x7)
(64-bit quad-pumped bus)
?v		 Socket 771 2x 32KB data (8-way)
2x 32KB instruction (8-way)
6MB on-Die shared L2 (24-way)		 410 million
0.045µm process
107mm² die
Xeon E5240 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit, VT)
February 27, 2008		 771 balls
3000MHz (333x9)
(64-bit quad-pumped bus)
?v		 Socket 771 2x 32KB data (8-way)
2x 32KB instruction (8-way)
6MB on-Die shared L2 (24-way)		 410 million
0.045µm process
107mm² die
Xeon X5260 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit, VT)
November 11, 2007 - {$851}		 771 balls
3333MHz (333x10)
(64-bit quad-pumped bus)
?v		 Socket 771 2x 32KB data (8-way)
2x 32KB instruction (8-way)
6MB on-Die shared L2 (24-way)		 410 million
0.045µm process
107mm² die
Xeon X5272 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit, VT)
November 11, 2007 - {$1172}		 771 balls
3400MHz (400x8.5)
(64-bit quad-pumped bus)
?v		 Socket 771 2x 32KB data (8-way)
2x 32KB instruction (8-way)
6MB on-Die shared L2 (24-way)		 410 million
0.045µm process
107mm² die
Xeon X52?? MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit, VT)
2008?		 771 balls
?MHz (?x?)
(64-bit quad-pumped bus)
?v		 Socket 771 2x 32KB data (8-way)
2x 32KB instruction (8-way)
6MB on-Die shared L2 (24-way)		 410 million
0.045µm process
107mm² die

Xeon L5310 MMX SSE SSE2 SSE3
(Clovertown)
(quad core (dual die), EM64T, NX bit)
March 12, 2006 - {$455}		 771 balls
1600MHz (266x6)
(64-bit quad-pumped bus)
?v		 Socket 771 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 4MB on-Die shared L2 (16-way)		 582 million
0.065µm process
284mm² die
Xeon L5318 MMX SSE SSE2 SSE3
(Clovertown)
(quad core (dual die), EM64T, NX bit)
September 5, 2007		 771 balls
1600MHz (266x6)
(64-bit quad-pumped bus)
?v		 Socket 771 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 4MB on-Die shared L2 (16-way)		 582 million
0.065µm process
284mm² die
Xeon L5320 MMX SSE SSE2 SSE3
(Clovertown)
(quad core (dual die), EM64T, NX bit)
March 12, 2007 - {$519}		 771 balls
1866MHz (266x7)
(64-bit quad-pumped bus)
?v		 Socket 771 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 4MB on-Die shared L2 (16-way)		 582 million
0.065µm process
284mm² die
Xeon L5335 MMX SSE SSE2 SSE3
(Clovertown)
(quad core (dual die), EM64T, NX bit, VT)
August 13, 2007 - {$380}		 771 balls
2000MHz (333x6)
(64-bit quad-pumped bus)
?v		 Socket 771 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 4MB on-Die shared L2 (16-way)		 582 million
0.065µm process
284mm² die
Xeon E5310 MMX SSE SSE2 SSE3
(Clovertown)
(quad core (dual die), EM64T, NX bit)
November 27, 2006 - {$455}		 771 balls
1600MHz (266x6)
(64-bit quad-pumped bus)
?v		 Socket 771 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 4MB on-Die shared L2 (16-way)		 582 million
0.065µm process
284mm² die
Xeon E5320 MMX SSE SSE2 SSE3
(Clovertown)
(quad core (dual die), EM64T, NX bit)
November 27, 2006 - {$690}		 771 balls
1866MHz (266x7)
(64-bit quad-pumped bus)
?v		 Socket 771 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 4MB on-Die shared L2 (16-way)		 582 million
0.065µm process
284mm² die
Xeon E5335 MMX SSE SSE2 SSE3
(Clovertown)
(quad core (dual die), EM64T, NX bit)
4Q 2006		 771 balls
2000MHz (333x6)
(64-bit quad-pumped bus)
?v		 Socket 771 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 4MB on-Die shared L2 (16-way)		 582 million
0.065µm process
284mm² die
Xeon E5345 MMX SSE SSE2 SSE3
(Clovertown)
(quad core (dual die), EM64T)
November 27, 2006 - {$851}		 771 balls
2333MHz (333x7)
(64-bit quad-pumped bus)
?v		 Socket 771 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 4MB on-Die shared L2 (16-way)		 582 million
0.065µm process
284mm² die
Xeon X5355 MMX SSE SSE2 SSE3
(Clovertown)
(quad core (dual die), EM64T)
November 27, 2006 - {$1172}		 771 balls
2666MHz (333x8)
(64-bit quad-pumped bus)
?v		 Socket 771 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 4MB on-Die shared L2 (16-way)		 582 million
0.065µm process
284mm² die
Xeon X5365 MMX SSE SSE2 SSE3
(Clovertown)
(quad core (dual die), EM64T)
August 13, 2007 - {$1172}		 771 balls
3000MHz (333x9)
(64-bit quad-pumped bus)
?v		 Socket 771 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 4MB on-Die shared L2 (16-way)		 582 million
0.065µm process
284mm² die

Xeon ??? MMX SSE SSE2 SSE3
(Whitefield)
(quad core, EM64T, NX bit, VT)
[cancelled]		 771 balls
?MHz (?x?)
(64-bit quad-pumped bus)
?v		 Socket 771 4x 32KB data (8-way)
4x 32KB instruction (8-way)
8x 2MB on-Die shared L2 (8-way)		 ? million
0.065µm process
?mm² die

Xeon L5408 MMX SSE SSE2 SSE3 SSE4
(Harpertown)
(quad core (dual die), EM64T, NX bit, VT)
February 27, 2008		 771 balls
2133MHz (266x8)
(64-bit quad-pumped bus)
?v		 Socket 771 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 6MB on-Die shared L2 (24-way)		 820 million
0.045µm process
214mm² die
Xeon L5410 MMX SSE SSE2 SSE3 SSE4
(Harpertown)
(quad core (dual die), EM64T, NX bit, VT)
March 25, 2008 - {$320}		 771 balls
2333MHz (333x7)
(64-bit quad-pumped bus)
?v		 Socket 771 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 6MB on-Die shared L2 (24-way)		 820 million
0.045µm process
214mm² die
Xeon L5420 MMX SSE SSE2 SSE3 SSE4
(Harpertown)
(quad core (dual die), EM64T, NX bit, VT)
March 25, 2008 - {$380}		 771 balls
2500MHz (333x7.5)
(64-bit quad-pumped bus)
?v		 Socket 771 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 6MB on-Die shared L2 (24-way)		 820 million
0.045µm process
214mm² die
Xeon E5405 MMX SSE SSE2 SSE3 SSE4
(Harpertown)
(quad core (dual die), EM64T, NX bit, VT)
November 11, 2007 - {$209}		 771 balls
2000MHz (333x6)
(64-bit quad-pumped bus)
?v		 Socket 771 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 6MB on-Die shared L2 (24-way)		 820 million
0.045µm process
214mm² die
Xeon E5410 MMX SSE SSE2 SSE3 SSE4
(Harpertown)
(quad core (dual die), EM64T, NX bit, VT)
November 11, 2007 - {$256}		 771 balls
2333MHz (333x7)
(64-bit quad-pumped bus)
?v		 Socket 771 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 6MB on-Die shared L2 (24-way)		 820 million
0.045µm process
214mm² die
Xeon E5420 MMX SSE SSE2 SSE3 SSE4
(Harpertown)
(quad core (dual die), EM64T, NX bit, VT)
November 11, 2007 - {$316}		 771 balls
2500MHz (333x7.5)
(64-bit quad-pumped bus)
?v		 Socket 771 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 6MB on-Die shared L2 (24-way)		 820 million
0.045µm process
214mm² die
Xeon E5430 MMX SSE SSE2 SSE3 SSE4
(Harpertown)
(quad core (dual die), EM64T, NX bit, VT)
November 11, 2007 - {$455}		 771 balls
2666MHz (333x8)
(64-bit quad-pumped bus)
?v		 Socket 771 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 6MB on-Die shared L2 (24-way)		 820 million
0.045µm process
214mm² die
Xeon E5440 MMX SSE SSE2 SSE3 SSE4
(Harpertown)
(quad core (dual die), EM64T, NX bit, VT)
November 11, 2007 - {$690}		 771 balls
2833MHz (333x8.5)
(64-bit quad-pumped bus)
?v		 Socket 771 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 6MB on-Die shared L2 (24-way)		 820 million
0.045µm process
214mm² die
Xeon E5450 MMX SSE SSE2 SSE3 SSE4
(Harpertown)
(quad core (dual die), EM64T, NX bit, VT)
November 11, 2007 - {$915}		 771 balls
3000MHz (333x9)
(64-bit quad-pumped bus)
?v		 Socket 771 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 6MB on-Die shared L2 (24-way)		 820 million
0.045µm process
214mm² die
Xeon E5462 MMX SSE SSE2 SSE3 SSE4
(Harpertown)
(quad core (dual die), EM64T, NX bit, VT)
November 11, 2007 - {$797}		 771 balls
2800MHz (400x7)
(64-bit quad-pumped bus)
?v		 Socket 771 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 6MB on-Die shared L2 (24-way)		 820 million
0.045µm process
214mm² die
Xeon E5472 MMX SSE SSE2 SSE3 SSE4
(Harpertown)
(quad core (dual die), EM64T, NX bit, VT)
November 11, 2007 - {$1022}		 771 balls
3000MHz (400x7.5)
(64-bit quad-pumped bus)
?v		 Socket 771 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 6MB on-Die shared L2 (24-way)		 820 million
0.045µm process
214mm² die
Xeon X5450 MMX SSE SSE2 SSE3 SSE4
(Harpertown)
(quad core (dual die), EM64T, NX bit, VT)
November 11, 2007 - {$851}		 771 balls
3000MHz (333x9)
(64-bit quad-pumped bus)
?v		 Socket 771 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 6MB on-Die shared L2 (24-way)		 820 million
0.045µm process
214mm² die
Xeon X5460 MMX SSE SSE2 SSE3 SSE4
(Harpertown)
(quad core (dual die), EM64T, NX bit, VT)
November 11, 2007 - {$1172}		 771 balls
3166MHz (333x9.5)
(64-bit quad-pumped bus)
?v		 Socket 771 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 6MB on-Die shared L2 (24-way)		 820 million
0.045µm process
214mm² die
Xeon X5472 MMX SSE SSE2 SSE3 SSE4
(Harpertown)
(quad core (dual die), EM64T, NX bit, VT)
November 11, 2007 - {$958}		 771 balls
3000MHz (400x7.5)
(64-bit quad-pumped bus)
?v		 Socket 771 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 6MB on-Die shared L2 (24-way)		 820 million
0.045µm process
214mm² die
Xeon X5482 MMX SSE SSE2 SSE3 SSE4
(Harpertown)
(quad core (dual die), EM64T, NX bit, VT)
November 11, 2007 - {$1279}		 771 balls
3200MHz (400x8)
(64-bit quad-pumped bus)
?v		 Socket 771 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 6MB on-Die shared L2 (24-way)		 820 million
0.045µm process
214mm² die
Xeon X54?? MMX SSE SSE2 SSE3 SSE4
(Harpertown)
(quad core (dual die), EM64T, NX bit, VT)
2008?		 771 balls
?MHz (400x?)
(64-bit quad-pumped bus)
?v		 Socket 771 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 6MB on-Die shared L2 (24-way)		 820 million
0.045µm process
214mm² die

Xeon MP ??? MMX SSE SSE2 SSE3
(Dunnington)
(six cores, EM64T, NX bit, VT)
2008?		 771 balls
?MHz (?x?)
(64-bit quad-pumped bus)
?v		 Socket 771 6x 32KB data (8-way)
6x 32KB instruction (8-way)
?MB on-Die shared L2 (?-way)		 ? million
0.045µm process
?mm² die


Xeon (Socket 604)
Intel
Processors		 Natural
State		 Sockets L1/L2 Cache
(Associativity)		 Transistors
Xeon MP L7345 MMX SSE SSE2 SSE3
(Tigerton)
(quad core, EM64T, NX bit, VT)
September 5, 2007 - {$2301}		 604 pins
1866MHz (266x7)
(64-bit quad-pumped bus)
?v		 Socket 604 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 4MB on-Die unified L2 (16-way)		 582 million
0.065µm process
284mm² die
Xeon MP E7210 MMX SSE SSE2 SSE3
(Tigerton)
(dual core, EM64T, NX bit, VT)
September 5, 2007 - {$1980}		 604 pins
2400MHz (266x9)
(64-bit quad-pumped bus)
?v		 Socket 604 2x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 4MB on-Die unified L2 (16-way)		 582 million
0.065µm process
284mm² die
Xeon MP E7220 MMX SSE SSE2 SSE3
(Tigerton)
(dual core, EM64T, NX bit, VT)
September 5, 2007 - {$1980}		 604 pins
2933MHz (266x11)
(64-bit quad-pumped bus)
?v		 Socket 604 2x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 4MB on-Die unified L2 (16-way)		 582 million
0.065µm process
284mm² die
Xeon MP E7310 MMX SSE SSE2 SSE3
(Tigerton)
(quad core, EM64T, NX bit, VT)
September 5, 2007 - {$856}		 604 pins
1600MHz (266x6)
(64-bit quad-pumped bus)
?v		 Socket 604 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 2MB on-Die unified L2 (8-way)		 582 million
0.065µm process
284mm² die
Xeon MP E7320 MMX SSE SSE2 SSE3
(Tigerton)
(quad core, EM64T, NX bit, VT)
September 5, 2007 - {$856}		 604 pins
2133MHz (266x8)
(64-bit quad-pumped bus)
?v		 Socket 604 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 2MB on-Die unified L2 (8-way)		 582 million
0.065µm process
284mm² die
Xeon MP E7330 MMX SSE SSE2 SSE3
(Tigerton)
(quad core, EM64T, NX bit, VT)
September 5, 2007 - {$856}		 604 pins
2400MHz (266x9)
(64-bit quad-pumped bus)
?v		 Socket 604 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 3MB on-Die unified L2 (12-way)		 582 million
0.065µm process
284mm² die
Xeon MP E7340 MMX SSE SSE2 SSE3
(Tigerton)
(quad core, EM64T, NX bit, VT)
September 5, 2007 - {$856}		 604 pins
2400MHz (266x9)
(64-bit quad-pumped bus)
?v		 Socket 604 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 4MB on-Die unified L2 (16-way)		 582 million
0.065µm process
284mm² die
Xeon MP X7350 MMX SSE SSE2 SSE3
(Tigerton)
(quad core, EM64T, NX bit, VT)
September 5, 2007 - {$2301}		 604 pins
2933MHz (266x11)
(64-bit quad-pumped bus)
?v		 Socket 604 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 4MB on-Die unified L2 (16-way)		 582 million
0.065µm process
284mm² die
Xeon MP X73xx MMX SSE SSE2 SSE3
(Tigerton)
(quad core, EM64T, NX bit, VT)
2008?		 604 pins
?MHz (266x?)
(64-bit quad-pumped bus)
?v		 Socket 604 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 4MB on-Die unified L2 (16-way)		 582 million
0.065µm process
284mm² die


Xeon (Socket ?)
Intel
Processors		 Natural
State		 Sockets L1/L2/L3 Cache
(Associativity)		 Transistors
Xeon ??? MMX SSE SSE2 SSE3 SSE4.2
(Gainestown)
192-bit DDR3 on-Die Registered PC? mem controller
(quad core, SMT Hyperthreading, EM64T, NX bit, VT)
2008?		 ? balls
?MHz (?x?)
(64-bit quad-pumped bus)
?v		 Socket ? 4x 32KB data (8-way)
4x 32KB instruction (4-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)		 731 million
0.045µm process
246mm² die

Xeon MP ??? MMX SSE SSE2 SSE3 SSE4.2
(Beckton)
192-bit DDR3 on-Die Registered PC? mem controller
(8 cores (dual die), SMT Hyperthreading, EM64T, NX bit, VT)
2009?		 ? balls
?MHz (?x?)
(64-bit quad-pumped bus)
?v		 Socket ? 8x 32KB data (8-way)
8x 32KB instruction (4-way)
8x 256KB on-Die unified L2 (8-way)
2x 8MB on-Die shared L3 (16-way)		 ? million
0.045µm process
?mm² die


Itanium
Intel
Processors		 Natural
State		 Sockets L1/L2/L3 Cache
(Associativity)		 Transistors
Itanium 733 MMX SSE
(Merced)
July, 2001		 418 pins
733MHz (133x5.5)
(64-bit dual-pumped bus)
?v		 PAC418 16KB data (4-way)
16KB instruction (4-way)
96KB on-Die unified L2 (6-way)
2MB or
4MB unified L3 (4-way)		 25 million
0.18µm process
~300mm² die
? million L3 {?µm - ?mm²} (2MB)
295 million L3 {?µm - ?mm²} (4MB)
Itanium 800 MMX SSE
(Merced)
July, 2001		 418 pins
800MHz (133x6.0)
(64-bit dual-pumped bus)
?v		 PAC418 16KB data (4-way)
16KB instruction (4-way)
96KB on-Die unified L2 (6-way)
2MB or
4MB unified L3 (4-way)		 25 million
0.18µm process
~300mm² die
? million L3 {?µm - ?mm²} (2MB)
295 million L3 {?µm - ?mm²} (4MB)

Itanium 2 900 MMX SSE
(McKinley)
July 8, 2002 - {$1338} (1.5MB)		 611 pins
900MHz (200x4.5)
(128-bit dual-pumped bus)
?v		 PAC611 16KB data
16KB instruction
256KB on-Die unified L2
1.5MB on-Die unified L3		 221 million
0.18µm process
463mm² die
Itanium 2 1.0G MMX SSE
(McKinley)
July 8, 2002 - {$?} (1.5MB)
July 8, 2002 - {$4226} (3MB)		 611 pins
1000MHz (200x5.0)
(128-bit dual-pumped bus)
?v		 PAC611 16KB data
16KB instruction
256KB on-Die unified L2
1.5MB or
3MB on-Die unified L3		 221 million
0.18µm process
463mm² die

Itanium 2 1.3G MMX SSE
(Madison) - copper chip
June 30, 2003 - {$1338}		 611 pins
1300MHz (200x6.5)
(128-bit dual-pumped bus)
?v		 PAC611 16KB data
16KB instruction
256KB on-Die unified L2
3MB on-Die unified L3		 ~500 million
0.13µm process
?mm² die
Itanium 2 1.4G MMX SSE
(Madison) - copper chip
June 30, 2003 - {$2247}		 611 pins
1400MHz (200x7.0)
(128-bit dual-pumped bus)
?v		 PAC611 16KB data
16KB instruction
256KB on-Die unified L2
4MB on-Die unified L3		 ~500 million
0.13µm process
?mm² die
Itanium 2 1.5G MMX SSE
(Madison) - copper chip
June 30, 2003 - {$3692} (6MB)
November, 2004 (4MB)		 611 pins
1500MHz (200x7.5)
(128-bit dual-pumped bus)
?v		 PAC611 16KB data
16KB instruction
256KB on-Die unified L2
4MB or
6MB on-Die unified L3		 ~500 million
0.13µm process
?mm² die

Itanium 2 1.6G MMX SSE
(Madison 9M)
November, 2004		 611 pins
1600MHz (200x8.0)
(128-bit dual-pumped bus)
?v		 PAC611 16KB data
16KB instruction
256KB on-Die unified L2
6MB or
9MB on-Die unified L3		 592 million
0.13µm process
432mm² die
Itanium 2 1.66G MMX SSE
(Madison 9M)
July, 2005		 611 pins
1666MHz (333x5.0)
(128-bit dual-pumped bus)
?v		 PAC611 16KB data
16KB instruction
256KB on-Die unified L2
6MB or
9MB on-Die unified L3		 592 million
0.13µm process
432mm² die

LV Itanium 2 1.0G MMX SSE
(Deerfield)
September 8, 2003 - {$744}		 611 pins
1000MHz (200x5.0)
(128-bit dual-pumped bus)
?v		 PAC611 16KB data
16KB instruction
256KB on-Die unified L2
1.5MB on-Die unified L3		 410 million
0.13µm process
374mm² die
LV Itanium 2 1.3G MMX SSE
(Deerfield)
November, 2004		 611 pins
1300MHz (200x6.5)
(128-bit dual-pumped bus)
?v		 PAC611 16KB data
16KB instruction
256KB on-Die unified L2
3MB on-Die unified L3		 410 million
0.13µm process
374mm² die
Itanium 2 1.4G MMX SSE
(Deerfield)
September 8, 2003 - {$1172} (1.5MB)
April 13, 2004 - {$1172} (3MB)		 611 pins
1400MHz (200x7.0)
(128-bit dual-pumped bus)
?v		 PAC611 16KB data
16KB instruction
256KB on-Die unified L2
1.5MB or
3MB on-Die unified L3		 410 million
0.13µm process
374mm² die
Itanium 2 1.6G MMX SSE
(Deerfield)
May, 2004 - {$2408}		 611 pins
1600MHz (200x8.0)
(128-bit dual-pumped bus)
?v		 PAC611 16KB data
16KB instruction
256KB on-Die unified L2
3MB on-Die unified L3		 410 million
0.13µm process
374mm² die
Itanium 2 1.6G MMX SSE
(Deerfield)
November, 2004 - {$2408}		 611 pins
1600MHz (266x6.0)
(128-bit dual-pumped bus)
?v		 PAC611 16KB data
16KB instruction
256KB on-Die unified L2
3MB on-Die unified L3		 410 million
0.13µm process
374mm² die

Itanium 9010 MMX SSE
(Montecito)
(Jackson Hyperthreading, VT)
July 18, 2006 - {$696}		 611 pins
1600MHz (266x6.0)
(128-bit dual-pumped bus)
?v		 PAC611 ?KB data
?KB instruction
1MB on-Die unified L2
6MB on-Die unified L3		 1720 million
0.09µm process
596mm² die
Itanium 9015 MMX SSE
(Montecito)
(dual core, Jackson Hyperthreading, VT)
July 18, 2006 - {$749}		 611 pins
1400MHz (200x7.0)
(128-bit dual-pumped bus)
?v		 PAC611 2x ?KB data
2x ?KB instruction
2x 1MB on-Die unified L2
2x 6MB on-Die unified L3		 1720 million
0.09µm process
596mm² die
Itanium 9020 MMX SSE
(Montecito)
(dual core, Jackson Hyperthreading, VT)
July 18, 2006 - {$910}		 611 pins
1420MHz (266x?)
(128-bit dual-pumped bus)
?v		 PAC611 2x ?KB data
2x ?KB instruction
2x 1MB on-Die unified L2
2x 6MB on-Die unified L3		 1720 million
0.09µm process
596mm² die
Itanium 9030 MMX SSE
(Montecito)
(dual core, Jackson Hyperthreading, VT)
July 18, 2006 - {$1552}		 611 pins
1600MHz (266x6.0)
(128-bit dual-pumped bus)
?v		 PAC611 2x ?KB data
2x ?KB instruction
2x 1MB on-Die unified L2
2x 4MB on-Die unified L3		 1720 million
0.09µm process
596mm² die
Itanium 9040 MMX SSE
(Montecito)
(dual core, Jackson Hyperthreading, VT)
July 18, 2006 - {$1980}		 611 pins
1600MHz (266x6.0)
(128-bit dual-pumped bus)
?v		 PAC611 2x ?KB data
2x ?KB instruction
2x 1MB on-Die unified L2
2x 9MB on-Die unified L3		 1720 million
0.09µm process
596mm² die
Itanium 9050 MMX SSE
(Montecito)
(dual core, Jackson Hyperthreading, VT)
July 18, 2006 - {$3692}		 611 pins
1600MHz (266x6.0)
(128-bit dual-pumped bus)
?v		 PAC611 2x ?KB data
2x ?KB instruction
2x 1MB on-Die unified L2
2x 12MB on-Die unified L3		 1720 million
0.09µm process
596mm² die

Itanium 9110N MMX SSE
(Montvale)
(Jackson Hyperthreading, VT)
October 31, 2007 - {$696}		 611 pins
1600MHz (266x6.0)
(128-bit dual-pumped bus)
?v		 PAC611 ?KB data
?KB instruction
1MB on-Die unified L2
6MB on-Die unified L3		 1720 million
0.09µm process
596mm² die
Itanium 9120N MMX SSE
(Montvale)
(dual core, Jackson Hyperthreading, VT)
October 31, 2007		 611 pins
1400MHz (200x7.0)
(128-bit dual-pumped bus)
?v		 PAC611 2x ?KB data
2x ?KB instruction
2x 1MB on-Die unified L2
2x 6MB on-Die unified L3		 1720 million
0.09µm process
596mm² die
Itanium 9130M MMX SSE
(Montvale)
(dual core, Jackson Hyperthreading, VT)
October 31, 2007		 611 pins
1666MHz (333x5.0)
(128-bit dual-pumped bus)
?v		 PAC611 2x ?KB data
2x ?KB instruction
2x 1MB on-Die unified L2
2x 4MB on-Die unified L3		 1720 million
0.09µm process
596mm² die
Itanium 9140M MMX SSE
(Montvale)
(dual core, Jackson Hyperthreading, VT)
October 31, 2007		 611 pins
1666MHz (333x5.0)
(128-bit dual-pumped bus)
?v		 PAC611 2x ?KB data
2x ?KB instruction
2x 1MB on-Die unified L2
2x 9MB on-Die unified L3		 1720 million
0.09µm process
596mm² die
Itanium 9140N MMX SSE
(Montvale)
(dual core, Jackson Hyperthreading, VT)
October 31, 2007		 611 pins
1600MHz (266x6.0)
(128-bit dual-pumped bus)
?v		 PAC611 2x ?KB data
2x ?KB instruction
2x 1MB on-Die unified L2
2x 9MB on-Die unified L3		 1720 million
0.09µm process
596mm² die
Itanium 9150M MMX SSE
(Montvale)
(dual core, Jackson Hyperthreading, VT)
October 31, 2007 - {$3692}		 611 pins
1666MHz (333x5.0)
(128-bit dual-pumped bus)
?v		 PAC611 2x ?KB data
2x ?KB instruction
2x 1MB on-Die unified L2
2x 12MB on-Die unified L3		 1720 million
0.09µm process
596mm² die
Itanium 9150N MMX SSE
(Montvale)
(dual core, Jackson Hyperthreading, VT)
October 31, 2007 - {$3692}		 611 pins
1600MHz (266x6.0)
(128-bit dual-pumped bus)
?v		 PAC611 2x ?KB data
2x ?KB instruction
2x 1MB on-Die unified L2
2x 12MB on-Die unified L3		 1720 million
0.09µm process
596mm² die
Itanium 9152M MMX SSE
(Montvale)
(dual core, Jackson Hyperthreading, VT)
4Q 2007		 611 pins
1666MHz (333x5.0)
(128-bit dual-pumped bus)
?v		 PAC611 2x ?KB data
2x ?KB instruction
2x 1MB on-Die unified L2
2x 12MB on-Die unified L3		 1720 million
0.09µm process
596mm² die
Itanium ??? MMX SSE
(Montvale)
(dual core, Jackson Hyperthreading)
2008?		 ? pins
?MHz (?x?)
(128-bit dual-pumped bus)
?v		 ? 2x ?KB data
2x ?KB instruction
2x 1MB on-Die unified L2
2x 12MB on-Die unified L3		 1720 million
0.065µm process
596mm² die

Itanium ??? MMX SSE
(Fanwood - 2-way)
(dual core, Jackson Hyperthreading)
2008?		 ? pins
?MHz (?x?)
(128-bit dual-pumped bus)
?v		 ? 2x ?KB data
2x ?KB instruction
2x ?MB on-Die unified L2
2x ?MB on-Die unified L3		 ? million
?µm process
?mm² die

Itanium ??? MMX SSE
(Millington - 2-way)
(dual core, Jackson Hyperthreading)
2008?		 ? pins
?MHz (?x?)
(128-bit dual-pumped bus)
?v		 ? 2x ?KB data
2x ?KB instruction
2x ?MB on-Die unified L2
2x ?MB on-Die unified L3		 ? million
?µm process
?mm² die

Itanium ??? MMX SSE
(Shavano)
(Jackson Hyperthreading)
2008?		 ? pins
?MHz (?x?)
(128-bit dual-pumped bus)
?v		 ? ?KB data
?KB instruction
?MB on-Die unified L2
?MB on-Die unified L3		 ? million
?µm process
?mm² die

Itanium ??? MMX SSE
(Tukwila)
(?-bit on-Die DDR? mem controller)
(quad core, Jackson Hyperthreading)
2008?		 ? pins
?MHz (?x?)
(?-bit ?-pumped bus)
?v		 ? 4x ?KB data
4x ?KB instruction
4x ?MB on-Die unified L2
4x ?MB on-Die unified L3		 >2000 million
0.065µm process
?mm² die

Itanium ??? MMX SSE
(Dimona)
(dual core, Jackson Hyperthreading)
2008?		 ? pins
?MHz (?x?)
(?-bit ?-pumped bus)
?v		 ? 2x ?KB data
2x ?KB instruction
2x ?MB on-Die unified L2
2x ?MB on-Die unified L3		 ? million
?µm process
?mm² die

Itanium ??? MMX SSE
(Poulson)
(multi core, Jackson Hyperthreading)
2008?		 ? pins
?MHz (?x?)
(?-bit ?-pumped bus)
?v		 ? 4x ?KB data
4x ?KB instruction
4x ?MB on-Die unified L2
4x ?MB on-Die unified L3		 ? million
?µm process
?mm² die


Notes:
  • µ - micron (millionth of a meter).
  • Unified caches hold both data and instructions; shared caches are unified caches shared by more than one core.
  • The dates listed are official introduction dates. It does not necessarily mean those processors were available in quantity on that date. Processor names that are italicized in blue indicate a tenative release date based on various news articles, speculation, and sometimes pure rumor.
  • The prices listed with each processor are its price at the chip's introduction in US dollars. All prices are for quantities of 1000.
  • All bus speeds listed on this page are actual speeds; not DDR. The Athlon, Core, and Merced chips all use a dual (2x) or quad-pumped (4x) bus that hits on the rising and falling edges of the clock, yielding a faster effective bus speed. The quad-pumped bus works similar to that of AGP 4x mode (it uses a synchronous signal to double strobe each rising and falling edge).
  • Rev C0 and later of the Opteron processors support PC3200; the earlier B3 revision (AG, AH, AI) supports up to PC2700.
  • Even though they have the same number of pins, Socket 940 and Socket AM2 CPUs are *NOT* interchangeable!

Fuente: http://users.erols.com/chare/current_cpus.htm
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